公开(公告)号：EP2529374A2

公开(公告)日：2012-12-05

申请号：EP11737663.2

申请日：2011-01-27

Applicant: Hewlett Packard Development Company, L.P. ,  University of Utah Research Foundation

Inventor： MURALIMANOHAR, Naveen ,  UDIPI, Aniruddha Nagendran ,  CHATTERJEE, Niladrish ,  BALASUBRAMONIAN, Rajeev ,  DAVIS, Alan Lynn ,  JOUPPI, Norman Paul

IPC: G11C11/4063 ,  G11C7/10 ,  G06F12/00

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0658 ,  G06F3/0673 ,  G06F11/1088 ,  G06F12/0802 ,  G06F12/0893 ,  G06F2212/1028 ,  G06F2212/3042 ,  G06F2212/305 ,  G11C5/04 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4082 ,  Y02D10/13

Abstract: An example apparatus includes a row address register to store a row address corresponding to a row in a memory array. The example apparatus also includes a row decoder coupled to the row address register to assert a signal on a wordline of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.

公开(公告)号：EP2486568A2

公开(公告)日：2012-08-15

申请号：EP10771243.2

申请日：2010-10-07

Applicant: Qualcomm Incorporated

Inventor： SUH, Jungwon

IPC: G11C5/00 ,  G11C8/12 ,  H01L25/065 ,  G11C16/20

CPC classification number: H01L25/0657 ,  G06F17/5077 ,  G11C5/02 ,  G11C8/12 ,  G11C16/20 ,  H01L23/481 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/15311

Abstract: A vertically stackable die having a chip identifier structure is disclosed. In a particular embodiment, a semiconductor device is disclosed that includes a die comprising a first through silicon via to communicate a chip identifier and other data. The semiconductor device also includes a chip identifier structure that comprises at least two through silicon vias that are each hard wired to an external electrical contact.

公开(公告)号：EP2454735A1

公开(公告)日：2012-05-23

申请号：EP10730021.2

申请日：2010-07-01

Applicant: Netlist, Inc.

Inventor： LEE , Hyun ,  BHAKTA, Jayesh, R.

IPC: G11C5/02 ,  G11C5/06

CPC classification number: G06F12/00 ,  G11C5/025 ,  G11C5/04 ,  G11C5/066 ,  G11C8/12

Abstract: A memory system and method utilizing one or more memory modules is provided. The memory module includes a plurality of memory devices and a controller configured to receive control information from a system memory controller and to produce module control signals. The memory module further includes a plurality of circuits, for example byte-wise buffers, which are configured to selectively isolate the plurality of memory devices from the system memory controller. The circuits are operable, in response to the module control signals, to drive write data from the system memory controller to the plurality of memory devices and to merge read data from the plurality of memory devices to the system memory controller. The circuits are distributed at corresponding positions separate from one another.

公开(公告)号：EP2443630A2

公开(公告)日：2012-04-25

申请号：EP10726382.4

申请日：2010-06-08

Applicant: Sandisk 3D LLC

Inventor： SEKAR, Deepak, C. ,  SCHUEGRAF, Klaus ,  SCHEUERLEIN, Roy

IPC: G11C13/00 ,  G11C8/12 ,  G11C7/00 ,  G06F12/06

CPC classification number: G11C13/0007 ,  G11C7/00 ,  G11C8/12 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0088 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72

Abstract: A storage system and method for operating the storage system that uses reversible resistance-switching elements is described. Techniques are disclosed herein for varying programming conditions to account for different resistances that memory cells have. These techniques can program memory cells in fewer attempts, which can save time and/or power. Techniques are disclosed herein for achieving a high programming bandwidth while reducing the worst case current and/or power consumption. In one embodiment, a page mapping scheme is provided that programs multiple memory cells in parallel in a way that reduces the worst case current and/or power consumption.

公开(公告)号：EP2404299A1

公开(公告)日：2012-01-11

申请号：EP10748249.9

申请日：2010-03-03

Applicant: MOSAID Technologies Incorporated

Inventor： KIM, Jin-Ki

IPC: G11C16/02 ,  G11C16/06 ,  G11C16/08

CPC classification number: G11C8/14 ,  G11C8/10 ,  G11C8/12 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C2211/5642

Abstract: A NAND flash memory device is disclosed. The NAND flash memory device includes a NAND flash memory array defined as a plurality of sectors. Row decoding is performed in two levels. The first level is performed that is applicable to all of the sectors. This can be used to select a block, for example. The second level is performed for a particular sector, to select a page within a block in the particular sector, for example. Read and program operations take place to the resolution of a page within a sector, while erase operation takes place to the resolution of a block within a sector.

公开(公告)号：EP2313890A1

公开(公告)日：2011-04-27

申请号：EP08795140.6

申请日：2008-08-08

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： AHN, Jung, Ho ,  JOUPPI, Norman, P. ,  SCHREIBER, Robert, S.

IPC: G11C8/00 ,  G06F12/08

CPC classification number: G11C5/04 ,  G06F12/06 ,  G06F12/0646 ,  G06F13/1684 ,  G06F2212/1028 ,  G11C8/12 ,  Y02D10/13 ,  Y02D10/14

Abstract: Various embodiments of the present invention are directed multi-core memory modules. In one embodiment, a memory module (500) includes memory chips, and a demultiplexer register (502) electronically connected to each of the memory chips and a memory controller. The memory controller groups one or more of the memory chips into at least one virtual memory device in accordance with changing performance and/or energy efficiency needs. The demultiplexer register (502) is configured to receive a command indentifying one of the virtual memory devices and send the command to the memory chips of the identified virtual memory device. In certain embodiments, the memory chips can be dynamic random access memory chips.

Abstract translation: 本发明的各种实施例涉及多核存储器模块。 在一个实施例中，存储器模块（500）包括存储器芯片以及电连接到每个存储器芯片和存储器控制器的解复用器寄存器（502）。 存储器控制器根据改变的性能和/或能量效率需求将一个或多个存储器芯片分组成至少一个虚拟存储器设备。 解复用器寄存器（502）被配置为接收识别虚拟存储器装置中的一个的命令，并将该命令发送到所识别的虚拟存储器装置的存储器芯片。 在某些实施例中，存储器芯片可以是动态随机存取存储器芯片。

公开(公告)号：EP2308050A1

公开(公告)日：2011-04-13

申请号：EP09770808.5

申请日：2009-06-19

Applicant: QUALCOMM Incorporated

Inventor： JUNG, Seong-Ook ,  SANI, Mehdi, Hamidi ,  KANG, Seung, H. ,  YOON, Sei, Seung

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C8/12 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1693 ,  Y10S977/933

Abstract: Systems, circuits and methods for controlling write operations in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A reduced bit cell size is achieved by arranging the source lines (SL) substantially in parallel with the word lines (WL) and substantially perpendicular to the bit lines (BL). Further, in one embodiment during a write operation, a high logic / voltage level is applied to the bit lines of unselected bit cells to prevent an invalid write operation.

公开(公告)号：EP1288961B1

公开(公告)日：2011-01-12

申请号：EP02252317.9

申请日：2002-03-28

Applicant: Fujitsu Semiconductor Limited

Inventor： Yamaguchi, Shusaku ,  Uchida, Toshiya ,  Yagishita, Yoshimasa ,  Bando, Yoshihide ,  Yada, Masahiro ,  Okuda, Masaki ,  Kobayashi, Hiroyuki ,  Hara, Kota ,  Fujioka, Shinya ,  Fujieda, Waichiro

IPC: G11C11/406 ,  G11C7/10 ,  G11C11/4096

CPC classification number: G11C7/1006 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4087 ,  G11C2211/4061 ,  G11C2211/4062

公开(公告)号：EP2226809A1

公开(公告)日：2010-09-08

申请号：EP10006714.9

申请日：2006-06-08

Applicant: Lexmark International, Inc.

Inventor： The designation of the inventor has not yet been filed

IPC: G11C8/12

CPC classification number: G11C16/349 ,  G11C8/12

Abstract: Electrical interfaces, addressing schemes, and command protocols allow for communications with memory modules in computing devices such as imaging and printing devices. Memory modules may be assigned an address through a set of discrete voltages. One, multiple, or all of the memory modules may be addressed with a single command, which may be an increment counter command, a write command, or a punch out bit field. The status of the memory modules may be determined by sampling a single signal that may be at a low, high, or intermediate voltage level.

Abstract translation: 电气接口，寻址方案和命令协议允许在计算设备与存储器模块通信：诸如成像和打印设备。 存储器模块可被分配通过一组离散的电压来解决。 一个，多个或所有存储器模块可以使用单个命令，其可以是递增计数器命令，写入命令，或击出比特字段来解决。 存储器模块的状态可以通过采样一个信号确实可在低，高或中间电压电平来确定的开采。

公开(公告)号：EP1906409B1

公开(公告)日：2010-09-08

申请号：EP07115184.9

申请日：2007-08-29

Applicant: Fujitsu Semiconductor Limited

Inventor： Kobayashi, Hiroyuki c/o FUJITSU LIMITED

IPC: G11C8/08 ,  G11C11/408

CPC classification number: G11C11/4085 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074