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    MICROCONTROLLER CIRCUIT, CORRESPONDING DEVICE, SYSTEM AND METHOD OF OPERATION
    31.
    发明公开
    MICROCONTROLLER CIRCUIT, CORRESPONDING DEVICE, SYSTEM AND METHOD OF OPERATION 审中-公开

    公开(公告)号：EP4057574A1

    公开(公告)日：2022-09-14

    申请号：EP22157917.0

    申请日：2022-02-22

    Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

    Inventor： RENNIG, Fred ,  DVORAK, Vaclav

    IPC: H04L12/40 ,  H03K7/08

    Abstract: A circuit (106) comprises a first (24a) and a second (24b) memory, a processing unit (21) and a timer (22). The processing unit generates a sequence of bits encoding a CAN frame and processes the sequence of bits to detect a sequence of PWM periods. Each PWM period has a dominant portion and a recessive portion, and a total duration. The processing unit stores values of a first parameter of the PWM periods into the first memory, and values of a second parameter of the PWM periods into the second memory, wherein the first and second parameter define a shape of the PWM periods. The timer comprises a first register (220) which reads from the first memory a value of the first parameter of a current PWM period. The timer comprises a counter (221) which increases a count number and resets the count number as a function of the value of the first register. A value of the first parameter of a subsequent PWM period is stored into the first register as a function of the value of the first register. The timer comprises a second register (222) which reads from the second memory a value of the second parameter of the current PWM period, and compares the count number of the counter circuit to such value. The second register drives an output pin (230) to a dominant (resp., recessive) value as a function of said comparing the count number of the counter circuit to the value of the second register. A value of the second parameter of a subsequent PWM period is stored into the second register in response to the count number reaching the value stored in the first or second register.

    A PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD
    33.
    发明公开
    A PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD 审中-公开

    公开(公告)号：EP4012984A1

    公开(公告)日：2022-06-15

    申请号：EP21212062.0

    申请日：2021-12-02

    Applicant: STMicroelectronics Application GmbH

    Inventor： RENNIG, Fred ,  NANDLINGER, Rolf

    IPC: H04L12/40

    Abstract: A processing system is described. The processing system comprises a first CAN XL communication system (50 1 ) and a second CAN XL communication system (50 2 ), wherein each CAN XL communication system (50 1 , 50 2 ) comprises a CAN XL protocol controller configured to generate a NRZ encoded transmission signal (TXD) and receive a NRZ encoded reception signal (RXD). Each CAN XL communication system (50 1 , 50 2 ) is configured to generate a first transmission signal (TXD1) by selecting the NRZ encoded transmission signal (TXD) or a PWM signal generated as a function of the NRZ encoded transmission signal (TXD).
    Specifically, the processing system (10a) comprises a bus (22) having a transmission node (TX2) and a reception node (RX2), wherein the bus (22) is configured to receive from each CAN XL communication system (50 1 , 50 2 ) a respective second transmission signal (TXD2) and drive the logic level at the transmission node (TX2) as a function of the logic levels of the second transmission signals (TXD2), and provide to each CAN XL communication system (50 1 , 50 2 ) a respective second reception signal (RXD2) having a logic level determined as a function of the logic level at the reception node (RX2). Moreover, the processing system comprises a switching circuit (24, 224, 306, 308, 52, 520) configured to support a plurality of modes, wherein, in a first mode, the switching circuit (24, 224, 306, 308, 52, 520) is configured to provide the NRZ encoded transmission signals (TXD) of the CAN XL communication systems (50 1 , 50 2 ) as the second transmission signals (TXD2) to the bus system (22), and provide the respective second reception signal (RXD2) received from the bus (22) to the CAN XL protocol controllers (300) of the CAN XL communication system (50 1 , 50 2 ).

    A CIRCUIT, CORRESPONDING SYSTEM, VEHICLE AND METHOD OF OPERATION
    35.
    发明公开
    A CIRCUIT, CORRESPONDING SYSTEM, VEHICLE AND METHOD OF OPERATION 审中-公开

    公开(公告)号：EP3920410A1

    公开(公告)日：2021-12-08

    申请号：EP21305639.3

    申请日：2021-05-17

    Applicant: STMicroelectronics (ALPS) SAS ,  STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

    Inventor： OCCHIPINTI, Aldo ,  ROUSSEL, Christophe ,  BURKHARDT, Fritz ,  TESTONI, Ignazio

    IPC: H02P29/024 ,  H02P29/028

    Abstract: A driver circuit (30) comprises a power supply pin (300) configured to receive a power supply voltage ( V s ), and a set of control pins (302a, 302b, 304a, 304b) configured to provide a set of control signals for controlling the switching activity of a set of switches of an h-bridge circuit. The set of switches of the h-bridge circuit comprises a pair of high-side switches and a pair of low-side switches.
    The driver circuit (30) comprises control circuitry (36) coupled (32a, 32b, 34a, 34b) to the control pins (302a, 302b, 304a, 304b) and configured to generate the control signals, and sensing circuitry (38, 360) coupled to the power supply pin (300) and configured to generate a detection signal indicative of said power supply voltage ( V s ) exceeding a threshold value.
    The control circuitry (36) is sensitive to the detection signal and is configured to generate said control signals to activate one of said pair of high-side switches and said pair of low-side switches and deactivate the other of said pair of high-side switches and said pair of low-side switches as a result of said detection signal being indicative of said power supply voltage ( V s ) exceeding said threshold value.

    A PROCESSING SYSTEM COMPRISING A QUEUED SERIAL PERIPHERAL INTERFACE, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD
    36.
    发明公开
    A PROCESSING SYSTEM COMPRISING A QUEUED SERIAL PERIPHERAL INTERFACE, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD 审中-公开

    公开(公告)号：EP3885924A1

    公开(公告)日：2021-09-29

    申请号：EP21162262.6

    申请日：2021-03-12

    Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

    Inventor： NANDLINGER, Mr. Rolf ,  OLEXA, Mr. Radek

    IPC: G06F13/40

    Abstract: A processing system (10a) comprising a queued Serial Peripheral Interface, SPI, circuit (30a) is described. The SPI circuit (30a) comprises a hardware SPI communication interface (36), an arbiter (34) and a plurality of interface circuits (32 0 ..32 n ). Specifically, each interface circuit (32 0 ..32 n ) comprises a transmission FIFO memory (320), a reception FIFO memory (322) and an interface control circuit (324). The interface control circuit (324) is configured to receive one or more first data packets from a digital processing circuit (102) and store the received one or more first data packets to the transmission FIFO memory (320). Next, the interface control circuit (324) sequentially reads the one or more first data packets from the transmission FIFO memory (320), extracts from the one or more first data packets at least one transmission data word (DATA), and provides the at least one extracted transmission data word (DATA) to the arbiter (34). In turn, interface control circuit (324) receives from the arbiter (34) a reception data word (RXDATA) and stores one or more second data packets to the reception FIFO memory (322), the one or more second data packets comprising the received reception data word (RXDATA). Finally, the interface control circuit (324) sequentially reads the one or more second data packets from the reception FIFO memory (322) and transmits the one or more second data packets to the digital processing circuit (102).

    AN ELECTRONIC DEVICE, A CORRESPONDING COMMUNICATION SYSTEM AND A VEHICLE COMPRISING THE SYSTEM
    37.
    发明公开
    AN ELECTRONIC DEVICE, A CORRESPONDING COMMUNICATION SYSTEM AND A VEHICLE COMPRISING THE SYSTEM 审中-公开

    公开(公告)号：EP3879730A1

    公开(公告)日：2021-09-15

    申请号：EP21158711.8

    申请日：2021-02-23

    Applicant: STMicroelectronics Application GmbH

    Inventor： RENNIG, Mr. Fred

    IPC: H04L1/00 ,  H04L12/40 ,  H04L12/403 ,  G06F11/07 ,  B60R16/023

    Abstract: An electronic device is configured for coupling to a communication bus to receive therefrom frames encoded according to a communication protocol. The electronic device comprises a check circuit sensitive to said frames and configured to perform a check (203, 204, 205) as to whether a received frame is encoded according to said communication protocol and is addressed to the electronic device. The electronic device comprises a frame counter circuit configured to count frames received during a monitoring time interval by increasing a frame count value as a result of a positive outcome of said check. The electronic device comprises a comparator circuit configured to set a status bit to a first value indicative of a first operating status of the electronic device as a result of the frame count value being equal (208) to a first threshold value, and to a second value indicative of a second operating status of the electronic device as a result of the frame count value being equal (210) to a second threshold value. The electronic device comprises a controller circuit configured to transmit (212a) over the communication bus a frame comprising the status bit, and configured to reset (214) the frame count value at the end of the monitoring time interval.
    The frame counter circuit comprises a modular arithmetic counter circuit having a certain bit depth. The frame count value is constrained to a modulus value of the modular arithmetic counter circuit.

    PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD
    39.
    发明公开
    PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD 审中-公开

    公开(公告)号：EP3657345A1

    公开(公告)日：2020-05-27

    申请号：EP19208829.2

    申请日：2019-11-13

    Applicant: STMicroelectronics Application GmbH

    Inventor： COLOMBO, Mr. Roberto

    IPC: G06F15/177 ,  G06F9/445 ,  G06F11/10

    Abstract: A processing system (10a) is described. The processing system comprises a plurality of configuration data client circuits (112), a hardware circuit (110) configured to change operation as a function of configuration data (CD) stored by the configuration data client circuits (112), a non-volatile memory (104) comprising the configuration data (CD) for the hardware circuit (110), and a hardware configuration circuit (108a) configured to read the configuration data (CD) from the non-volatile memory (104) and transmit the configuration data (CD) to the configuration data client circuits (112) . The configuration data (CD) are stored in the non-volatile memory (104) in the form of data packets (DCF1..DCFn) comprising an address (ADR) and respective configuration data (CD).
    Specifically, the hardware configuration circuit (108a) is configured to sequentially read (1080) the data packets (DCF1..DCFn) from the non-volatile memory (104), select a target configuration data client circuit (112), and transmit (1082) via a first data signal (DATA) the configuration data (CD) included in the data packet (DCFi) to a respective target configuration data client circuit (112). Moreover, the hardware configuration circuit (108a) is configured to receiving via a second data signal (DATA', ADR') the configuration data (CD) stored by the target configuration data client circuit (112) and the respective address associated with the target configuration data client circuit (112). Thus, the hardware configuration circuit (108a) may comparing (1090) the configuration data and address received from the target configuration data client circuit (112) with the content of the data packets (DCF1..DCFn) read from the non-volatile memory (104), and possibly generate an error signal.

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