公开(公告)号：EP0293833A2

公开(公告)日：1988-12-07

申请号：EP88108695.3

申请日：1988-05-31

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Masuoka, Hideaki

IPC分类号： H03K19/092 ,  H03K19/086 ,  H03K19/013

CPC分类号： H03K19/0136 ,  H03K19/086

摘要： An output circuit comprising a differential amplifier circuit (Q1, Q2) for providing a pair of complementary output signals corresponding to an input signal (ei) supplied to first and second signal input terminals (T1, T2) thereof, an output transistor (Q3) having a base connected to one output node (A) of the differential amplifier circuit, a collector connected to a first power source potential supply terminal (Vcc), and an emitter connected to a signal output terminal (T3), a current mirror circuit (Q4, Q5) having a current input terminal (X) connected to a current source (I2) and a current output terminal connected to the signal output terminal (T3), and a capacitor (C1) connected between the other output node (B) of the differential amplifier circuit and the current input terminal (X) of the current mirror circuit.

摘要翻译： 一种输出电路，包括：差分放大器电路（Q1，Q2），用于提供与提供给其第一和第二信号输入端（T1，T2）的输入信号（ei）对应的一对互补输出信号;输出晶体管（Q3） 具有连接到差分放大器电路的一个输出节点（A）的基极，连接到第一电源电位端子（Vcc）的集电极和连接到信号输出端子（T3）的发射极，电流镜像电路 具有连接到电流源（I2）的电流输入端子（X）和连接到信号输出端子（T3）的电流输出端子的Q4，Q5）和连接在另一个输出节点（B）之间的电容器（C1） 的差分放大器电路和电流镜电路的电流输入端（X）。

公开(公告)号：EP0262156A4

公开(公告)日：1988-07-14

申请号：EP87900937

申请日：1987-01-12

申请人： MOTOROLA INC

发明人： HUNTINGTON ROBERT CHARLES

IPC分类号： G05F1/56 ,  G05F1/46 ,  G05F3/24 ,  H03H11/24 ,  H03K19/00 ,  H03K19/0185 ,  H03K19/0948 ,  H03K19/092 ,  H03K3/01 ,  H03K3/353

CPC分类号： G05F3/242 ,  G05F1/465 ,  H03H11/245 ,  H03K19/018521

公开(公告)号：EP0102110B1

公开(公告)日：1987-11-04

申请号：EP83201132.4

申请日：1983-08-01

申请人： Philips Electronics N.V.

发明人： Smith, Douglas Duke

IPC分类号： H03K19/092 ,  H03K19/003 ,  H03F1/30

CPC分类号： H03K19/01806 ,  H03K19/00376

公开(公告)号：EP0179310A3

公开(公告)日：1987-10-28

申请号：EP85112409

申请日：1985-10-01

申请人： International Business Machines Corporation

发明人： Grimes, Dwight Wilson

IPC分类号： H03K19/00 ,  H03K19/094 ,  H03K19/082 ,  H03K19/092

CPC分类号： H03M5/16

摘要： 57 A communications interface for transferring data from a first binary logic circuit (11) to a second binary logic circuit (12) by using a trinary logic transmission channel. The first set of binary logic signals is converted into a first set of binary control signals which, in turn, control trinary drivers (18) connected to the transmission channel. The trinary drivers drive the transmission channel to one of three discrete voltage levels as opposed to one of two levels in binary systems. Trinary receivers (21) are located on the second binary logic circuit and are connected to the trinary transmission channel. The receivers produce a second set of binary control signals which are translated into a second set of binary logic signals for use by the second binary logic circuit.

公开(公告)号：EP0216756A4

公开(公告)日：1987-07-30

申请号：EP84904268

申请日：1984-11-02

申请人： ADVANCED MICRO DEVICES INC

发明人： THOMPSON MICHAEL D

IPC分类号： H01L27/02 ,  H03K19/018 ,  H03K19/173 ,  H03K19/092

CPC分类号： H03K19/01812 ,  H01L27/0207 ,  H03K19/173

摘要： An integrated circuit device (10 in Fig. 2; 105 in Fig. 5) containing internal logic and/or memory circuitry (19; 114, 115) is provided with means to receive multiple inputs at the voltage levels of different logic families (Pi-Pi) and with means to provide multiple outputs at the voltage levels of different logic families (Pj-Pn). On-chip input translators (15, 17; 106, 108, 110, 112) receive the inputs at the level of a given logic family and translate to the level required by the internal logic and/or memory circuitry. After performance of logic and/or memory functions, on-chip output translators (16, 18; 107, 109, 111, 113) translate the otput of the internal logic and/or memory circuitry and provide external outputs at the voltage levels of different logic families. The internal logic and/or memory circuitry may be of a single logic family or may be composed of several logic families. On-chip translators may also be added between internal logic and/or memory circuitry of different families (116, 117).

摘要翻译： 包含内部逻辑和/或存储器电路（19; 114,115）的集成电路器件（图2中的10;图5中的105）设置有用于接收不同逻辑系列的电压电平的多个输入（Pi -Pi）以及用不同逻辑系列（Pj-Pn）的电压电平提供多个输出的装置。 片上输入转换器（15,17; 106,108,110,112）以给定逻辑族的级别接收输入并转换为内部逻辑和/或存储器电路所需的级别。 在执行逻辑和/或存储器功能之后，片上输出转换器（16,18; 107,109,111,113）转换内部逻辑和/或存储器电路的输出并提供处于不同电压电平的外部输出 逻辑系列。 内部逻辑和/或存储器电路可以是单个逻辑系列或可以由几个逻辑系列组成。 片上转换器也可以添加在不同系列的内部逻辑和/或存储器电路之间（116,117）。

公开(公告)号：EP0132005A3

公开(公告)日：1987-04-22

申请号：EP84200999

申请日：1984-07-10

申请人： N.V. Philips' Gloeilampenfabrieken

发明人： West, Jeffery Alma ,  Fletcher, Thomas Dale

IPC分类号： H03K19/092

CPC分类号： H03K19/01806

摘要： A bipolar signal translator contains a pair of transistors (Q1 and 02) arranged as a current mirror with their emitters coupled to a voltage supply (VEE) by way of a pair of impedance elements (R4 and R5) that improve stability. Their collectors are coupled through another pair of impedance elements (R1 and R2) to an input transistor (Q4 and Q5) and to a device circuit (D1 and D2, D3 and D4, or Q4). The collector of one of the current-mirror transistors (02) is coupled to the base of an ouput transistor (03) whoe collector is preferably coupled through an output impedance element (R3) to a current-control transistor (Q6) that improves power utilization.

公开(公告)号：EP0203700A2

公开(公告)日：1986-12-03

申请号：EP86302923.7

申请日：1986-04-18

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Williams, Bertrand Jeffery ,  Wilson, Stanley

IPC分类号： H03K19/092 ,  H03K19/013

CPC分类号： H03K3/288 ,  H03K19/0136 ,  H03K19/01812

摘要： A logic level translator having high switching speeds for converting ECL logic levels into TTL logic levels includes a pair of input transistors for receiving ECL input logic level signals and an output transistor for generating TTL output logic level signals. Current mirror transistors are interconnected between the input transistors and the output transistor for turning on and off the output transistor. High-pass networks are coupled to the current mirror transistors for increasing its transient response so as to facilitate turning on and off quickly the output transistor. The TTL output logic levels have a relatively small propagation delay responsive to transitions of the ECL input logic level signals.

摘要翻译： 具有用于将ECL逻辑电平转换为TTL逻辑电平的高开关速度的逻辑电平转换器包括用于接收ECL输入逻辑电平信号的一对输入晶体管和用于产生TTL输出逻辑电平信号的输出晶体管。 电流镜晶体管在输入晶体管和输出晶体管之间互连，用于导通和关断输出晶体管。 高通网络耦合到电流镜晶体管，用于增加其瞬态响应，以便于快速地导通和关断输出晶体管。 响应于ECL输入逻辑电平信号的转换，TTL输出逻辑电平具有相对较小的传播延迟。

公开(公告)号：EP0173288A3

公开(公告)日：1986-07-30

申请号：EP85110704

申请日：1985-08-26

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Hara, Hiroyuki c/o Patent Division ,  Nakamura, Michinori c/o Patent Division ,  Sugimoto, Yasuhiro c/o Patent Division

IPC分类号： H03K19/092

CPC分类号： H03K19/017527 ,  H03K19/01707

摘要： A voltage level converting circuit includes first and second potential terminals (P1, P2) between which a power source voltage is applied, first and second terminals (IN1, IN2) for receiving an input signal and an inverted input signal, a differential amplifier (T1, T2, IS) including npn transistors (T1, T2) whose conduction states are controlled by the input signal and the inverted input signal, and an output circuit for generating an output logic signal corresponding to the output voltage of the differential amplifier (T1, T2, IS). The output circuit of this voltage level converting circuit has a current path connected in series between the first and second potential terminals (P1, P2) by way of a constant current source (M3), and includes a MOS transistor (M2) whose conduction state is controlled by the ouptut voltage of the differential amplifier (T1, T2, IS).

公开(公告)号：EP0090099A3

公开(公告)日：1985-11-06

申请号：EP82201536

申请日：1982-12-03

申请人： N.V. Philips' Gloeilampenfabrieken

发明人： Bellavance, Joseph Thomas

IPC分类号： H01L27/02 ,  H01L27/06 ,  H03K19/092

CPC分类号： H01L27/0244 ,  H01L27/0233 ,  H01L27/075 ,  H03K19/01806 ,  H03K19/0915

摘要： In an integrated logic circuit having an inverter transistor with a signal input connected to its control electrode and one or more signal outputs each coupled via a diode to one of its main electrodes an interface or translation transistor is added. Preferably an ISL clamped NPN transistor and a PNP interface transistor are merged together in a single semiconductive isolated island. The two transistors are laterally separated from each other along a semiconductive surface of the island, which also includes one or more metallic elements forming individual Schottky barrier contact diodes with the semiconductive surface. The PNP transistor provides translation between an ISL logic gate and a TTL logic gate. One of the Schottky diodes may be used in combination with the NPN transistor as an active pull down for an output transistor of the TTL logic gate.

公开(公告)号：EP0092156A3

公开(公告)日：1985-01-23

申请号：EP83103570

申请日：1983-04-13

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Nagano, Katsumi

IPC分类号： H03K19/092

CPC分类号： H03K19/01818

摘要： In input interface circuit (11) for a logic device which has a first transistor (Q1) whose base is supplied with an input signal (VI) and whose emitter is grounded through first and second resistors (R1, R2) and a second transistor (Q2) whose base is supplied with the potential of the node of the first and second resistors (R1, R2) and whose collector sends forth a logic signal. This input interface circuit (11) is further provided with a third resistor (Q3) connected between the second resistor (R2) and ground and a third transistor (Q3) whose current path is connected in parallel to the third resistor (R3) and whose base is connected to the collector of the second transistor (Q2).