公开(公告)号：EP0815505A1

公开(公告)日：1998-01-07

申请号：EP96907837.0

申请日：1996-03-15

申请人： Telefonaktiebolaget LM Ericsson (publ)

发明人： HINTUKAINEN, Kari, Anders

IPC分类号： G06F12 ,  G06F5

CPC分类号： G06F5/065 ,  G06F2205/064

摘要： The invention relates to an arrangement and a method respectively for handling or getting access to a digital buffer in a digital buffer memory (JBUM) wherein to each digital buffer a set of pointers is arranged in a reference memory (REFM). The arrangement comprises a register arrangement (JBSR, JBER) defining the position of a digital buffer in the digital buffer memory (JBUM), an offset value, an address calculation arrangement and an operating address register (JBAR). For each of the pointers in a set relating to a digital buffer, a separate pointer register (JBSR, JBER, JBIR, JBOR) is provided and address data is input and stored substantially at the same time in each pointer register corresponding to a set of pointers. The subsequent address for reading/writting in the digital buffer memory (JBUM) is calculated and stored in at least the operating address register (JBAR).

公开(公告)号：EP0378195B1

公开(公告)日：1997-04-09

申请号：EP90100444.0

申请日：1990-01-10

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Shobatake, Yasuro ,  Kumaki, Yoshinari

IPC分类号： G06F5/06 ,  G06F13/18

CPC分类号： H04Q11/0478 ,  G06F5/065 ,  G06F13/18 ,  G06F2205/064 ,  G06F2205/066 ,  H04L2012/5651 ,  H04L2012/5681

公开(公告)号：EP0680633A4

公开(公告)日：1996-03-13

申请号：EP94906690

申请日：1994-01-18

申请人： CONNER PERIPHERALS INC

发明人： CORNABY STEPHEN R

IPC分类号： G06F9/46 ,  G06F5/06 ,  G06F7/78 ,  G06F9/22 ,  G06F9/06 ,  G06F9/34 ,  G06F9/345 ,  G06F9/35 ,  G06F12/08 ,  G06F12/10 ,  G06F15/40

CPC分类号： G06F7/78 ,  G06F5/06 ,  G06F2205/064

摘要： A queue system comprising a plurality of queues (20-23) where each is defined by a set of criteria, the queue system comprises a plurality of header registers (1-3) where each header register defines a queue in the queue system and a plurality of task registers where each task register can be associated with each queue (20-23) in the queue system. Each header register has a unique address and contains a previous field and a next field. Each previous field and said next field store the address of another register in a given queue such that each queue is formed in a double link structure. Control means is provided for dynamically assigning task registers to queues (20-23) by controlling the addresses in the previous and next fields in each header and task registers such that each of said task registers is always assigned to a queue in the queue system.

公开(公告)号：EP0360899B1

公开(公告)日：1993-08-04

申请号：EP88116010.5

申请日：1988-09-28

申请人： Siemens Nixdorf Informationssysteme Aktiengesellschaft

发明人： Hülters, Hubert

IPC分类号： G06F5/06

CPC分类号： G06F5/14 ,  G06F2205/064

公开(公告)号：EP0419066A2

公开(公告)日：1991-03-27

申请号：EP90309468.8

申请日：1990-08-30

申请人： International Business Machines Corporation

发明人： Bonevento, Francis Michael ,  McGovern, Joseph Patrick ,  Thomas, Eugene Mitchell

IPC分类号： G06F15/16 ,  G06F13/42 ,  G06F9/46

CPC分类号： G06F9/3869 ,  G06F5/06 ,  G06F13/4226 ,  G06F2205/064

摘要： A microprocessor system which includes a processor unit with system memory and a separate buffer memory, one or more subsystem adapter units with memory, optional I/O devices which may attach to the adapters, and a bus interface. The memory in the processor and the memory in the adapters are used by the system as a shared memory (106,112) which is configured as a distributed FIFO circular queue (a pipe). Unit to unit asynchronous communication is accomplished by placing control elements (104,116) on the pipe which represent requests, replies, and status information. The units (622,624) send and receive control elements (104,116) independent of the other units which allows free flowing asynchronous delivery of control information and data between units (622,624). The shared memory (106,112) can be organised as pipe pairs between each pair of units to allow full duplex operation by using one pipe for outbound control elements (104,116) and the other pipe for inbound control elements (104,116). The control elements (104,116) have standard fixed header fields with variable fields following the fixed header. The fixed header allows a common interface protocol to be used by different hardware adapters. The combination of the pipe and the common interface protocol allows many different types of hardware adapters to asynchronously communicate, resulting in higher overall throughput due to lower interrupt overhead.

摘要翻译： 一种微处理器系统，包括与系统存储器和一个单独的缓冲存储器，一个或多个子系统适配器单元与存储器，其可以附连到适配器可选I / O设备，以及总线接口的处理器单元。 在处理器中的存储器，并在适配器存储器中的系统所使用作为被配置为分布式FIFO循环队列（配管）的共享存储器（106.112）所有。 单元到单元的异步通信通过将在管控制元件（104.116），其代表请求，应答和状态信息来实现的。 作为单元（622.624）发送和接收（104.116）独立，其允许控制信息和数据单元之间自由流动的异步传送（622.624）的其它单元的控制元件。 共享存储器（106.112）可以被组织成各对单元之间配管对以允许全双工操作，通过使用一个管用于出站控制元件（104.116）和其他管的入站控制元件（104.116）。 所述控制元件（104.116）具有可变域标准的固定头字段继固定报头。 所述固定报头允许通过不同的硬件适配器一起使用的通用接口协议。 管和共用接口协议的组合允许许多不同类型的硬件适配器的异步通信，在更高的总吞吐量所得由于较低的中断开销。

公开(公告)号：EP0141753A3

公开(公告)日：1988-11-02

申请号：EP84402214

申请日：1984-11-05

申请人： DIGITAL EQUIPMENT CORPORATION

发明人： Altman, Barbara H. ,  Bruckert, William F. ,  Dellicicchi, Alfred J.

IPC分类号： G06F13/28 ,  G06F05/00

CPC分类号： G06F5/065 ,  G06F2205/064 ,  G06F2205/066

摘要： A data handling system for transferring data between two units, the data being transferred in blocks of a selected number of data words, up to predetermined maximum number. A buffer stores the data being transferred. The buffer includes a plurality of stages (70, 71, 72, 73) arranged serially from an input end (70) to an output end (73), the number of stages being equal in number to the predetermined maximum number of data words that may be transferred in a block. If the number of data words being transferred is less than the predetermined maximum number, as indicated by a control signal (S0, S1) from the unit transmitting the data, the buffer either receives the data in the stage a number of stages from the output end, or transmits the data from the stage a number of stages from the input end, equal to the number of words being transferred in the block.

公开(公告)号：EP0108338A2

公开(公告)日：1984-05-16

申请号：EP83110685.1

申请日：1983-10-26

申请人： International Business Machines Corporation

发明人： Tallman, Peter Heermance

IPC分类号： G06F15/40

CPC分类号： G06F7/78 ,  G06F5/06 ,  G06F17/30958 ,  G06F2205/064

摘要： This queue management method enables a single chained queue (10) to have parallel operations by plural element insertion routines and one deletion routine which may be simultaneously executing asynchronously on plural processors for deleting an element, while inserting one or more anchor-pointed elements. This is done by providing a dequeueing lock (11) which is only examined by a program routine (50) which is to delete an element, but is not examined by any program routine which is to make an insertion of an anchor-pointed element into the queue using a System/370 compare and swap instruction. The embodiments provide efficient processing in a non-pure LIFO queue, which is non-pure because the queue can, at the user's option, be used for either LIFO or non-LIFO dequeueing . No lock is used on the queue when inserting anchor-pointed elements. A special case of non-LIFO processing is FIFO (first-in/first-out) processing, which finds the last element in the queue (10) as the required element.

摘要翻译： 这种队列管理方法使得单个链接队列（10）能够通过多个元素插入例程和一个删除例程进行并行操作，该删除例程可以同时在多个处理器上异步地执行以删除元素，同时插入一个或多个锚点元素。 这是通过提供一个仅由程序例程（50）检查的出列锁（11），该程序例程（50）将删除元素，但不被任何程序例程检查，该程序例程将使锚点元素插入 使用System / 370比较和交换指令的队列。这些实施例在非纯粹的LIFO队列中提供有效的处理。 这是非纯的，因为队列可以根据用户的选择用于LIFO或非LIFO出列。 插入锚点元素时，队列上不使用锁。 非LIFO处理的一种特殊情况是FIFO（先进先出）处理，它将队列（10）中的最后一个元素作为必需元素。

公开(公告)号：EP3077914B1

公开(公告)日：2018-12-26

申请号：EP14796612.1

申请日：2014-10-21

申请人： Oracle International Corporation

发明人： AGGARWAL, Uttam

IPC分类号： G06F13/38 ,  G06F3/06

CPC分类号： G06F5/065 ,  G06F5/06 ,  G06F13/28 ,  G06F13/385 ,  G06F15/17331 ,  G06F2205/064 ,  G06F2205/067 ,  H04L67/2871

摘要： A system and method can support input/output (I/O) virtualization in a computing environment. The system can comprise a free buffer pool in a memory. An I/O device operates to use the free buffer pool to store disk read data received from a physical host bus adaptor (HBA). The free buffer pool can contain a two-dimensional linked list and a one-dimensional linked list. Each entry of the two-dimensional linked list contains multiple packet buffers in consecutive memory locations, and each entry of the one-dimensional linked list contains a single packet buffer.

公开(公告)号：EP2862061A2

公开(公告)日：2015-04-22

申请号：EP13803692.6

申请日：2013-06-13

申请人： Soft Machines, Inc.

发明人： ABDALLAH, Mohammad

IPC分类号： G06F9/38

CPC分类号： G06F9/30043 ,  G06F5/14 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3842 ,  G06F2205/063 ,  G06F2205/064

摘要： An out of order processor. The processor includes a virtual load store queue for allocating a plurality of loads and a plurality of stores, wherein more loads and more stores can be accommodated beyond an actual physical size of the load store queue of the processor; wherein the processor allocates other instructions besides loads and stores beyond the actual physical size limitation of the load/store queue; and wherein the other instructions can be dispatched and executed even though intervening loads or stores do not have spaces in the load store queue.

公开(公告)号：EP1207640A3

公开(公告)日：2005-10-19

申请号：EP01308917.2

申请日：2001-10-19

申请人： Altima Communications, Inc.

发明人： Chang, Michael ,  Sokol, Michael

IPC分类号： H04J3/06 ,  H04L12/56

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F5/065 ,  G06F2205/064 ,  H04J3/0697 ,  H04L49/103 ,  H04L49/205 ,  H04L49/254 ,  H04L49/351 ,  H04L2012/5665 ,  H04L2012/5681 ,  H04L2012/5682 ,  Y02D10/126

摘要： A system for reducing clock speed and power consumption in a network chip. The system has a core that transmits and receives signals at a first clock speed. A receive buffer is in communication with the core and configured to transmit the signals to the core at the first clock speed. A transmit buffer is in communication with the core and configured to receive signals from the core at the first clock speed. A sync is configured to receive signals in the receive buffer at a second clock speed and to transmit the signals from the transmit buffer at the second clock speed. The sync is in communication with the transmit buffer and the receive buffer.