公开(公告)号：EP2476195B1

公开(公告)日：2017-12-27

申请号：EP10815437.8

申请日：2010-09-03

申请人： Ricoh Company, Limited

发明人： UEDA, Yasuo ,  TOKUDA, Masashi ,  TSUKAGOSHI, Toshihiro

IPC分类号： H02M1/38 ,  H03K5/151 ,  H03K17/16 ,  H02M7/537

CPC分类号： H02M1/38 ,  H03K5/1515 ,  H03K17/16

摘要： A dead-time generating circuit includes a constant current circuit; a current generating circuit generating a capacitor-charge current; and a control circuit receiving a dead time control signal and a comparator signal. The control circuit generates a dead time generating signal based on the dead time control signal and the comparator signal, and a charge/discharge signal based on the dead time generating signal. Charging or discharging of a capacitor is controlled by the capacitor-charge current in accordance with the charge/discharge signal. A voltage of the capacitor is compared with a threshold voltage in order to generate a comparator signal when the voltage of the capacitor exceeds the threshold voltage. The control circuit generates the charge/discharge signal for a duration starting from a time when the delay time has elapsed from the rise or fall timing of the dead time control signal until the control circuit receives the comparator signal.

公开(公告)号：EP2920882A1

公开(公告)日：2015-09-23

申请号：EP13798501.6

申请日：2013-11-15

申请人： Microchip Technology Incorporated

发明人： STEEDMAN, Sean, Stacy ,  LUNDSTRUM, Zeke ,  GROZA, Cristian, Nicolae ,  COPACIAN, Sebastian, Dan ,  DARMAWASKITA, Hartono

IPC分类号： H03K5/151 ,  H03K7/08

CPC分类号： G06F1/06 ,  G06F12/00 ,  G06F13/1694 ,  H03K5/05 ,  H03K5/1515 ,  H03K7/08 ,  H03L7/089 ,  H03L7/10 ,  Y02D10/14

摘要： A complementary output generator (COG) module generates at least two complementary outputs determined by rising and falling event sources. In a simple configuration of the COG module, the rising and falling event sources are the same signal which is a signal having the desired period and duty cycle. The COG module converts this single signal input into dual complementary outputs. The frequency and duty cycle of the dual outputs substantially match those of the single input signal. Blanking and deadband times may be introduced between the complementary outputs, and the dual complementary outputs may also be phase delayed. In addition the COG module may provide up to four outputs for controlling half and full-wave bridge power applications.

公开(公告)号：EP2751635A4

公开(公告)日：2015-08-19

申请号：EP12827303

申请日：2012-08-24

申请人： R2 SEMICONDUCTOR INC

发明人： BROWN JAMES E C ,  ROTHENBERG BRET

IPC分类号： G05F1/10 ,  H02M1/08 ,  H02M1/38 ,  H03K5/151

CPC分类号： H02M1/38 ,  H02M1/08 ,  H03K5/1515

摘要： Embodiments for at least one method and apparatus for controlling timing of switch control signals of a switching voltage regulator disclosed. One method includes generating a regulated output voltage based upon a switching voltage, generating the switching voltage through controlled closing and opening of a series switch element and a shunt switch element, and controlling, by a delay block, the closing and opening of the series switch element and a shunt switch element. The delay block control includes receiving, by the delay block, a timing signal, generating a one of a series switch control signal and a shunt switch control signal by controllably delaying the timing signal with a first delay, and generating one other of the series switch control signal and the shunt switch control signal by inverting, and controllably delaying the timing signal with a second delay.

公开(公告)号：EP2901552A1

公开(公告)日：2015-08-05

申请号：EP13728197.8

申请日：2013-06-12

申请人： Robert Bosch GmbH

发明人： EITRICH, Frank-Thomas

IPC分类号： H03K5/151 ,  H03K5/1252

摘要： The invention relates to a logic gate (30) for the symmetrization of at least two input signals, which comprises a non-inverting input (11), an inverting input (12) and an output (19). The value present on the output (19) corresponds to the inverse of the value present on the inverting input (12). According to the invention, the output (19) is activated only when the value present on the non-inverting input (11) likewise corresponds to the inverse of the value present on the inverting input (12). The invention further relates to a logic gate system which comprises at least two logic gates (30).

公开(公告)号：EP2409205B1

公开(公告)日：2015-06-17

申请号：EP10711305.2

申请日：2010-03-18

申请人： QUALCOMM Incorporated

发明人： QIAO, Dongjiang ,  BOSSU, Frederic

IPC分类号： G06F1/06 ,  H03K5/151 ,  H03K23/54

CPC分类号： G06F1/06 ,  H03K23/667 ,  H03K23/68

公开(公告)号：EP2806560A1

公开(公告)日：2014-11-26

申请号：EP14368023.9

申请日：2014-05-15

申请人： Dialog Semiconductor GmbH

发明人： Mykhaylo, Teplechuk

IPC分类号： H03K17/16 ,  H03K5/151 ,  H03K17/687 ,  H03K5/1252

CPC分类号： H03K17/162 ,  H03K5/1252 ,  H03K5/1515 ,  H03K17/6872

摘要： Automatic and robust anti-shoot-through glitch-free operation of half-bridge control pre-driver and power stage circuits have been achieved by using multiple feedback control signals. These feedback signals are taken both from the gates of power devices on high side and low sides and from the gates of one or more devices on both high side and low side that enable power device ON state. No duty cycle limitation is required of the input signal. The control logic uses NAND/NOR RS latches. The solution disclosed can readily be scaled to higher order of feedback loops providing even greater level of robustness

摘要翻译： 通过使用多个反馈控制信号，实现了半桥控制前驱动器和功率级电路的自动和鲁棒的防穿透无毛刺操作。 这些反馈信号既从高侧和低侧的功率器件的栅极以及从高侧和低侧的一个或多个器件的栅极获取，从而使电源器件处于接通状态。 输入信号不需要占空比限制。 控制逻辑使用NAND / NOR RS锁存器。 所公开的解决方案可以容易地扩展到提供甚至更高级别的鲁棒性的反馈环路的更高阶

公开(公告)号：EP1936789A3

公开(公告)日：2011-11-30

申请号：EP07018348.8

申请日：2007-09-19

申请人： Dr. Johannes Heidenhain GmbH

发明人： Huber, Norbert

IPC分类号： H02M1/08 ,  H02M7/538 ,  H02M1/38 ,  H03K17/28 ,  H03K5/151 ,  H03K17/26

CPC分类号： H02M1/08 ,  H02M1/38 ,  H02M7/538 ,  H03K7/08 ,  H03K17/26 ,  H03K17/28

摘要： Es wird ein Umrichter mit einer Verzögerungsschaltung für ein am Eingang (e) der Verzögerungsschaltung (D) anliegendes PWM-Signal (A, nA) beschrieben, durch die steigende Flanken des PWM-Signals (A, nA) um eine Einschaltverzögerung (Ton) und fallende Flanken des PWM-Signals (A, nA) um eine Ausschaltverzögerung (Toff) verzögert werden, zum Bilden eines am Ausgang (a) der Verzögerungsschaltung (D) anliegenden Ansteuersignals (A', nA') für ein Halbleiterschaltelement (TH, TL). Die Verzögerungsschaltung (D) enthält zwei Widerstände (R1, R2), zwei Kondensatoren (C1, C2), eine Diode (D1) und einen Komparator (K) und ist damit besonders einfach zu realisieren.

公开(公告)号：EP1104110B1

公开(公告)日：2011-09-21

申请号：EP00310447.8

申请日：2000-11-24

申请人： FUJITSU LIMITED

发明人： Tamura, Hirotaka ,  Kibune, Masaya

IPC分类号： H03L7/081 ,  H04L7/033 ,  H03K5/13 ,  H03K5/151

CPC分类号： G06G7/12 ,  H03K5/13 ,  H03K5/133 ,  H03K5/151 ,  H03K2005/00026 ,  H03K2005/0013 ,  H03K2005/00208 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0891 ,  H04L7/033

公开(公告)号：EP1183780B1

公开(公告)日：2010-10-20

申请号：EP01917058.8

申请日：2001-03-05

申请人： NXP B.V.

发明人： BOEZEN, Hendrik ,  VAN DEN HEUVEL, Abraham, K.

IPC分类号： H03K19/003 ,  H03K19/00 ,  H03K5/151

CPC分类号： H03K5/1515

摘要： An electronic circuit having first (VSS) and second (VDD) power supply terminals and comprising a first digital driver (DRV) and a further digital driver (DRVF). The digital drivers (DRV, DRVF) are arranged for driving capacitive loads such as charge pump capacitors (CP1, CP2) of a charge pump (CHGP). The first digital driver (DRV) comprises a first field effect transistor (T1) having a source coupled to the first power supply terminal (VSS), a drain coupled for driving the first charge pump capacitor (CP1), and a gate; a second field effect transistor (T2) having a source coupled to the second power supply terminal (VDD), a drain coupled to the drain of the first field effect transistor (T1), and a gate; a first capacitor (C1) coupled between the gate of the first field effect transistor (T1) and an input terminal (CLK) for receiving a digital input signal (UCLK); and a second capacitor (C2) coupled between the gate of the second field effect transistor (T2) and the input terminal (CLK). The further digital driver (DRVF) is constructed in a similar way as the digital driver (DRV). DC paths are formed between the gates of field effect transistors (T1 - T4) and the supply terminals (VSS, VDD). Owing to the special construction of the digital drivers (DRV, DRVF), there is never a short-circuit current between the digital drivers (DRV, DRVF). As a result, the digital drivers (DRV, DRVF) have a very high power efficiency.

公开(公告)号：EP1104110A3

公开(公告)日：2003-10-08

申请号：EP00310447.8

申请日：2000-11-24

申请人： FUJITSU LIMITED

发明人： Tamura, Hirotaka ,  Kibune, Masaya

IPC分类号： H03L7/081 ,  H04L7/033 ,  H03K5/13 ,  H03K5/151

CPC分类号： G06G7/12 ,  H03K5/13 ,  H03K5/133 ,  H03K5/151 ,  H03K2005/00026 ,  H03K2005/0013 ,  H03K2005/00208 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0891 ,  H04L7/033

摘要： A phase-combining circuit for combining cyclic timing waveforms that have been phase-controlled by control signals based on three or more input signals (ϕ1 to ϕ4) of different phases, has a weight signal generating circuit and a weighting circuit (5). The weight signal generating circuit generates weights (W1 to W4) according to the control signals, and the weighting circuit (5) gives the weights to the respective input signals (ϕ1 to ϕ4), with a polarity of positive or negative for each one signal. Alternatively, two or more input signals have weights applied to them each of which varies in both a positive and negative range.