公开(公告)号：EP4199109A1

公开(公告)日：2023-06-21

申请号：EP22211736.8

申请日：2022-12-06

申请人： Commissariat à l'énergie atomique et aux énergies alternatives

发明人： CHARBONNIER, Jean ,  ASSOUS, Myriam ,  BEDECARRATS, Thomas ,  RAMBAL, Nils ,  VINET, Maud

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L21/78 ,  B82Y10/00

摘要： Réalisation d'un dispositif quantique à Qbits de spin comprenant un substrat de type semi-conducteur sur isolant, le substrat étant doté d'une couche semi-conductrice superficielle (12), la couche semi-conductrice superficielle étant disposée sur une couche isolante (11), la couche isolante étant agencée sur une face supérieure d'une couche de support semi-conductrice (10). Le dispositif est muni d'au moins un composant formé d'un ou plusieurs ilots quantiques s'étendant dans la couche semi-conductrice superficielle (12), les ilots quantiques sont induits par des électrodes de grilles (20A, 20B), dites avants, contrôlant l' électrostatique des ilots quantiques et étant disposées sur la couche semi-conductrice superficielle. En plus le composant est doté en outre d'une grille de contrôle électrostatique arrière, ladite grille de contrôle arrière étant formée d'une couche conductrice (119) tapissant des parois latérales et un fond d'une ouverture (517) traversant ladite couche de support semi-conductrice depuis une face inférieure de ladite couche de support opposée à ladite face supérieure jusqu'à ladite couche isolante (11) du substrat, ladite couche conductrice (119) étant disposée, au fond de l'ouverture (517), contre et avantageusement en contact avec ladite couche isolante du substrat, ladite couche conductrice (119) étant disposée contre et en contact avec ladite couche de support semi-conductrice au niveau desdites parois latérales de ladite ouverture. L'ouverture (517) dans laquelle la grille arrière est formée est gravée de manière concomitante avec des tranchées de découpage (111).

公开(公告)号：EP4195288A1

公开(公告)日：2023-06-14

申请号：EP22205784.6

申请日：2022-11-07

申请人： INTEL Corporation

发明人： Majhi, Prashant ,  Murthy, Anand ,  Killampalli, Aravind S.

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78 ,  H01L29/165 ,  H01L21/225 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/66 ,  B82Y10/00

摘要： An integrated circuit includes a body of semiconductor material. A source or drain region includes semiconductor material in contact with the body, where the semiconductor material of the source or drain region includes an outer region having a dopant concentration that is greater than a remaining region of the source or drain region, the outer region defining multiple contact surfaces of the source or drain region and extending into the source or drain region to a depth of at least 1 nm. A contact comprising a metal is on the multiple contact surfaces of the source or drain region. The dopant concentration of the outer region is continuous along the entire interface between the contact and the outer region, according to an example.

公开(公告)号：EP4191679A1

公开(公告)日：2023-06-07

申请号：EP21212174.3

申请日：2021-12-03

申请人： Imec VZW

发明人： Chan, Boon Teik ,  Hellings, Geert ,  Chehab, Bilal ,  Ryckaert, Julien ,  Horiguchi, Naoto

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L21/336 ,  H01L29/775 ,  H01L27/088 ,  H01L29/417 ,  B82Y10/00

摘要： According to an aspect, there is provided a method for forming a FET device, comprising:
forming a preliminary device structure comprising a fin structure comprising a layer stack comprising channel layers and non-channel layers alternating the channel layers, and a deposited layer along a first side of the fin structure and a dummy structure along a second side of the fin structure;
forming a mask line;
forming along a first side of the fin structure a source and drain trench in the deposited layer;
forming a set of source and drain cavities in the layer stack, by etching the fin structure from the source trench and the drain trench;
forming a source body and a drain body comprising a respective common body portion a set of prongs protruding from the respective common body portion into the source and drain cavities;
embedding the mask line in a cover material and removing the mask structure;
forming a gate trench by etching the dummy structure;
forming a set of gate cavities in the layer stack by etching the fin structure from the gate trench; and
forming a gate body comprising a common gate body portion in the gate trench and a set of gate prongs protruding from the common gate body portion into the gate cavities

公开(公告)号：EP3164889B1

公开(公告)日：2023-06-07

申请号：EP15707943.5

申请日：2015-03-04

发明人： MARCUS, Charles ,  KROGSTRUP, Peter ,  JESPERSEN, Thomas Sand ,  NYGÅRD, Jesper ,  PETERSSON, Karl ,  LARSEN, Thorvald ,  KUEMMETH, Ferdinand

IPC分类号： H01L29/41 ,  H01L39/08 ,  H01L39/02 ,  B82Y40/00 ,  B82Y10/00 ,  H01L39/06 ,  H01L39/24 ,  H01L39/22 ,  H01L29/45 ,  H01L29/43 ,  H01L29/06 ,  H01L29/66 ,  C23C14/18 ,  C23C14/50 ,  C23C14/54 ,  H01L29/04 ,  C23C14/22

公开(公告)号：EP4184586A1

公开(公告)日：2023-05-24

申请号：EP22199552.5

申请日：2022-10-04

申请人： INTEL Corporation

发明人： BOMBERGER, Cory ,  MURTHY, Anand ,  SHAH, Rushabh ,  NASKAR, Sudipto

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L21/336 ,  H01L29/775 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/32

摘要： An integrated circuit (IC) device (800B, 800C), and a method of forming the same. The IC device includes a transistor device comprising a multilayer stack that has a plurality of channel layers (Si channel) including a semiconductor material; a gate structure wrapped at least partially around the channel layers, the gate structure including a metal; an epitaxial source structure (112B) at a first lateral end of the multilayer stack; an epitaxial drain structure (112B) at a second lateral end of the multilayer stack opposite the first lateral end; and inner spacers (120B, 120C) between the gate structure and respective ones of the source structure and the drain structure, wherein the epitaxial source and drain structures are formed prior to removing the sacrificial semiconductor layers and forming the inner spacers, because of which the source and drain structures do not exhibit crystallographic defects extending from the inner spacers. The source drain structures furthermore exert compressive strain on the channel layers.

公开(公告)号：EP2942817B1

公开(公告)日：2023-05-24

申请号：EP15166618.7

申请日：2011-11-23

发明人： Kuhn, Kelin J. ,  Kim, Seiyon ,  Rios, Rafael ,  Cea, Stephen M. ,  Giles, Martin D. ,  Cappellani, Annalisa ,  Rakshit, Titash ,  Chang, Peter ,  Rachmady, Willy

IPC分类号： H01L29/775 ,  H01L29/786 ,  H01L29/66 ,  H01L21/336 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/423 ,  H01L29/06

公开(公告)号：EP3372564B1

公开(公告)日：2023-05-10

申请号：EP18000284.2

申请日：2009-02-27

发明人： Koike, Akio ,  Iwahashi, Yasutomi ,  Kikugawa, Shinya ,  Tachibana, Yuko

IPC分类号： C03B19/14 ,  C03C3/06 ,  C03C4/00 ,  B82Y10/00 ,  B82Y40/00 ,  C03C3/076 ,  G03F1/24 ,  G03F7/20

公开(公告)号：EP4168948A1

公开(公告)日：2023-04-26

申请号：EP21829452.8

申请日：2021-06-21

申请人： Psiquantum Corp.

发明人： WANG, Albert

IPC分类号： G06N10/00 ,  G06T11/00 ,  B82Y10/00

公开(公告)号：EP4160689A1

公开(公告)日：2023-04-05

申请号：EP22183728.9

申请日：2022-07-08

申请人： Samsung Electronics Co., Ltd.

发明人： KIM, Hyuncheol ,  KIM, Yongseok ,  WOO, Dongsoo ,  LEE, Kyunghwan

IPC分类号： H01L27/24 ,  H01L45/00 ,  G11C13/00 ,  B82Y10/00

摘要： A variable resistance memory device including a stack including insulating sheets (220) and conductive sheets (210), which are alternatingly stacked on a substrate, the stack including a vertical hole (VH) vertically penetrating therethrough, a bit line on the stack, a conductive pattern (320) electrically connected to the bit line and vertically extending in the vertical hole (VH), and a resistance varying layer (310) between the conductive pattern (320) and an inner side surface of the stack defining the vertical hole (VH) may be provided. The resistance varying layer (310) may include a first carbon nanotube (CNT1) electrically connected to the conductive sheets (210), and a second carbon nanotube (CNT2) electrically connected to the conductive pattern (320s).

公开(公告)号：EP4156283A1

公开(公告)日：2023-03-29

申请号：EP22191316.3

申请日：2022-08-19

申请人： INTEL Corporation

发明人： GHANI, Tahir ,  MURTHY, Anand ,  DEWEY, Gilbert ,  KOBRINSKY, Mauro ,  BOMBERGER, Cory ,  HARATIPOUR, Nazila ,  NANDI, Debaleena ,  SHAH, Rushabh

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/66 ,  H01L29/775 ,  H01L29/45 ,  B82Y10/00 ,  H01L29/36

摘要： PMOS gate-all-around integrated circuit structures having confined p-type epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. P-type epitaxial source or drain structures (358, 359, 360, 364, 366) are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise i) a first PMOS epitaxial (pEPI) region of germanium and boron (358), ii) a second pEPI region of silicon, germanium and boron (359) on the first pEPI region at a contact location, iii) a capping layer comprising silicon (360) over the second pEPI region. A conductive contact material (366) comprising titanium is on the capping layer.The resulting source or drain structure exhibits an ultra-low contact resistance and is thermally stable. Preferably the B-11 boron isotope is used in the source or drain structure.