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    PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD
    54.
    发明公开
    PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD 审中-公开

    公开(公告)号：EP4254130A1

    公开(公告)日：2023-10-04

    申请号：EP23158857.5

    申请日：2023-02-27

    Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics International N.V.

    Inventor： COLOMBO, Roberto ,  SHARMA, Vivek Mohan

    IPC: G06F1/24

    Abstract: A processing system (10a) is described. The processing system comprises a reset circuit (116a) receiving a reset-request signal (RT' 115 ) provided by a power-supply monitoring circuit (115) and further reset-request signals (RT' 102 , RT' 120 , RT' RP ) provided by a microprocessor (1020, one or more further circuits (106, 110, 120) and/or a terminal (RP) of the processing system (10a). The reset circuit (116a) generates a combined reset-request signal (CRT) by combining (1162, 1166) the reset-request signals (RT' 115 , RT' 102 , RT' 120 , RT' RP ). In response to the combined reset-request signal (CRT), the processing system (10a) is configured (116a, 118) to execute various phases in sequence. Specifically, in a reset phase, the reset circuit (116a) executes a reset of the processing system (10a). In a diagnostic phase, a diagnostic circuit (118) executes one or more tests of the processing system (10a). In a software runtime phase, the microprocessor (1020) is started. A hardware test circuit (40, 420, 422) is configured to repeat various operations during the diagnostic phase for each of the further reset-request signals (RT' 102 , RT' 120 , RT' RP ). Specifically, the test circuit (40) masks (1004) the combined reset-request signal (CRT), asserts the respective further reset-request signal (RT' 102 , RT' 120 , RT' RP ) and de-asserts all other further reset-request signals (RT' 102 , RT' 120 , RT' RP ). Next, in response to determining that the combined reset-request signal (CRT) is de-asserted, the test circuit (40) generates a signal (STATE) indicating a failure of said reset circuit (116a).

    ELECTRONIC SYSTEM FOR DRIVING LIGHT SOURCES AND METHOD OF DRIVING LIGHT SOURCES
    56.
    发明公开
    ELECTRONIC SYSTEM FOR DRIVING LIGHT SOURCES AND METHOD OF DRIVING LIGHT SOURCES 审中-公开

    公开(公告)号：EP4064794A3

    公开(公告)日：2023-01-18

    申请号：EP22305278.8

    申请日：2022-03-11

    Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMicroelectronics S.r.l. ,  STMicroelectronics Application GmbH

    Inventor： GAERTNER, Manuel ,  SIRITO-OLIVIER, Philippe ,  TORRISI, Giovanni Luca ,  URBITSCH, Thomas ,  ROUSSEL, Christophe ,  BURKHARDT, Fritz

    IPC: H05B45/37 ,  H05B45/325 ,  H05B45/10 ,  H05B45/46 ,  H05B45/52 ,  H05B47/25 ,  H02M3/335 ,  B60Q11/00 ,  B60Q1/14

    Abstract: A system (100') comprises a microcontroller unit (102) and a driver device (101) coupled (105) to the microcontroller unit (102) to receive data therefrom. The driver device (101) comprises a plurality of output supply pins (101C 1 , ..., 101C n ) and is configured to selectively propagate (30 1 , ..., 30 n ) a supply voltage ( V BAT ) to the output supply pins (101C 1 , ..., 101C n ) to provide respective pulse-width modulated supply signals ( V BAT,1 , ..., V BAT,n ) at the output supply pins (101C 1 , ..., 101C n ). The driver device (101) is configured to compute respective duty-cycle values of the pulse-width modulated supply signals ( V BAT,1 , ..., V BAT,n ) as a function of the data received from the microcontroller unit (102) . The system further comprises a plurality of lighting devices (31 1,1 , ..., 31 1,m , 31 n ) coupled to the plurality of output supply pins (101C 1 , ..., 101C n ). The plurality of lighting devices (31 1,1 , ..., 31 1,m , 31 n ) comprises at least one subset of lighting devices (31 1,1 , ..., 31 1,m ) coupled to a same output supply pin (101C 1 ) in the plurality of output supply pins (101C 1 , ..., 101C n ). The system further comprises a set of respective electronic switches coupled in series to the lighting devices in the at least one subset of lighting devices (31 1,1 , ..., 31 1,m ). The microcontroller unit (102) is configured to individually control the electronic switches via respective control signals ( P 1,1 , ..., P 1,m ) to individually adjust a brightness of the lighting devices in the at least one subset of lighting devices (31 1,1 , ..., 31 1,m ).

    A CURRENT SUPPLY SYSTEM AND A METHOD OF OPERATING SAID CURRENT SUPPLY SYSTEM
    57.
    发明公开
    A CURRENT SUPPLY SYSTEM AND A METHOD OF OPERATING SAID CURRENT SUPPLY SYSTEM 审中-公开

    公开(公告)号：EP4002958A1

    公开(公告)日：2022-05-25

    申请号：EP21205675.8

    申请日：2021-10-29

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

    Inventor： TAGLIAVIA, Donato ,  POLISI, Vincenzo ,  TRECARICHI, Calogero Andrea ,  MAMMOLITI, Francesco Nino ,  BARTHEL, Jochen ,  BERAN, Ludek

    IPC: H05B45/347 ,  H05B45/46 ,  H05B45/14

    Abstract: A current supply system for strings of solid-state light sources (34) is disclosed. The current supply system comprises a plurality of terminals (OUT1..OUTn), wherein each of the terminals (OUT1..OUTn) is configured to be connected via a respective current regulator or limiter (32) to a first output terminal of a voltage source (20) and via a respective string of solid-state light sources (34) to a second output terminal of the voltage source (20). A control circuit (40) is configured to generate a reference signal ( V ref ) for the voltage source (20), wherein the reference signal is indicative of a requested output voltage ( V out ) to be generated by the voltage source (20) between the first and the second output terminals of the voltage source (20).
    In particular, the control circuit (40) comprises:
    - a digital feed-forward control circuit (408, 410, 412) configured to compute a digital feed-forward regulation value ( V out_req ) indicative of a requested output voltage by determining a maximum voltage drop ( V LED_MAX ) at the strings of solid-state light sources (34),
    -a digital feed-back control circuit (414) configured to determine (1030) a minimum voltage drop ( V 32_MIN ) at the current regulators or limiters (32) and determine a digital feed-back correction value as a function of the minimum voltage drop ( V 32_MIN ), and
    - a control circuit (40) configured to set the reference signal ( V ref ) after a start-up as a function of the digital feed-forward regulation value ( V out_req ) and then correct the reference signal ( V ref ) as a function of the digital feed-back correction value.

    A METHOD OF OPERATING A COMMUNICATION BUS, CORRESPONDING SYSTEM, DEVICES AND VEHICLE
    58.
    发明公开
    A METHOD OF OPERATING A COMMUNICATION BUS, CORRESPONDING SYSTEM, DEVICES AND VEHICLE 审中-公开

    公开(公告)号：EP3913864A1

    公开(公告)日：2021-11-24

    申请号：EP21172208.7

    申请日：2021-05-05

    Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

    Inventor： RENNIG, Fred ,  DVORAK, Vaclav ,  BERAN, Ludek

    IPC: H04L12/40

    Abstract: A method of operating a CAN bus comprises coupling a first device (10) and second devices (20 1 , ..., 20 n ) to the CAN bus (30) via respective CAN transceiver circuits. The method comprises configuring the first device as a communication master device to transmit first messages carrying operation data message portions indicative of operations for implementation by the second devices, and second messages addressed to the second devices, the second messages conveying identifiers identifying respective ones of the second devices to which the second messages are addressed requesting respective reactions towards the first device within respective expected reaction intervals. The method comprises configuring the second devices as communication slave devices to receive the first messages transmitted from the first device, read respective operation data message portions in said operation data message portions and implement respective operations as a function of the respective operation data message portions read, and to receive the second messages transmitted from the first device and react thereon within said respective expected reaction intervals by transmitting reaction messages towards the first device. The method comprises configuring said respective CAN transceiver circuits to set the CAN bus to a recessive level during transmission of said messages via the CAN bus by the respective first device or second device.

    DIGITAL INTERFACE CIRCUIT FOR ANALOG-TO-DIGITAL CONVERTER
    59.
    发明公开
    DIGITAL INTERFACE CIRCUIT FOR ANALOG-TO-DIGITAL CONVERTER 审中-公开

    公开(公告)号：EP3761183A1

    公开(公告)日：2021-01-06

    申请号：EP20183631.9

    申请日：2020-07-02

    Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics International N.V.

    Inventor： TRIVEDI, Nirav Prashantkumar ,  ATAL, Sandip ,  NANDLINGER, Rolf

    IPC: G06F13/28 ,  H03M1/12 ,  H03M1/38

    Abstract: An analog-to-digital conversion system (500) is described. The analog-to-digital conversion system (500) comprises an analog-to-digital converter (100), a multiplexer (200), wherein the multiplexer has a plurality of input channels that are configured to be coupled to a plurality of analog input signals (201), and wherein an output terminal of the multiplexer (203) is coupled to an input terminal of the ADC (102). The analog-to-digital conversion system (500) comprises also a digital interface circuit (300) configured to be coupled between the ADC (100) and a processor (400). The digital interface circuit (300) is configured to receive a sequence of commands (CMD0 FRM..CMD3 FRM) from the processor (400), wherein each command of the sequence of commands (CMD0 FRM..CMD3 FRM) comprises a channel number (ADC CH NUM) that indicates an input channel (201) of the multiplexer (200), wherein channel numbers contained in the sequence of commands define a channel sequence. The digital interface circuit (300) stores the sequence of commands (CMD0 FRM..CMD3 FRM) in a command First-In First-Out, FIFO, buffer (305) of the digital interface circuit (300) and sends the sequence of commands (CMD0 FRM..CMD3 FRM) stored in the command FIFO buffer (305) to the ADC (100) for a first time to control operation of the ADC, wherein analog input signals at input channels of the multiplexer (200) specified by the channel sequence are converted into digital data sequentially for the first time. Moreover, the digital interface circuit (300) sends the same sequence of commands (CMD0 FRM..CMD3 FRM) stored in the command FIFO buffer (305) to the ADC (100) for a second time, wherein the analog input signals at the input channels of the multiplexer (200) specified by the channel sequence are converted into digital data sequentially for the second time.

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