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232 条记录 (耗时 0.019 秒)

    Integrated circuit device
    52.
    发明授权
    Integrated circuit device 失效
    集成电路设备

    公开(公告)号：EP0145595B1

    公开(公告)日：1990-05-16

    申请号：EP84402512.2

    申请日：1984-12-06

    申请人： FUJITSU LIMITED

    发明人： Takemae, Yoshihiro ,  Nakano, Tomio ,  Nakano, Masao ,  Sato, Kimiaki

    IPC分类号： G11C17/00 ,  H01L23/52 ,  G06F11/20

    CPC分类号： G11C29/785 ,  G11C17/16 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device having a fuse-blown type ROM for storing information concerning defective bits for the replacement of defective bits in a semiconductor memory device, etc., with redundant bits. The integrated circuit device comprises fuses for constituting the ROM, pads for supplying a melting current to the fuses, and PN junctions each being formed, for example, by a semiconductor substrate and a diffusion layer formed on the semiconductor substrate. Each of the fuses is melted by applying voltage to a circuit connecting the PN junction, the fuse, and the pad so that the PN junction is forward biased, thereby supplying a large current to the fuse.

    Random access memory device formed on a semiconductor substrate having an array of memory cells divided in sub-arrays
    55.
    发明公开
    Random access memory device formed on a semiconductor substrate having an array of memory cells divided in sub-arrays 失效
    在具有分散在子阵列中的记忆细胞阵列的半导体基底上形成的随机存取器件

    公开(公告)号：EP0182353A3

    公开(公告)日：1989-08-16

    申请号：EP85114695.1

    申请日：1985-11-19

    申请人： FUJITSU LIMITED

    发明人： Takemae, Yoshihiro

    IPC分类号： G11C5/02 ,  G11C8/00 ,  G11C11/406

    CPC分类号： G11C11/40603 ,  G11C7/1045 ,  G11C8/12 ,  G11C8/14 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/408

    摘要： ( A random access memory (DRAM) device formed on a semiconductor substrate having an array of memory cells (MC) which are divided in several sub-arrays (MCA 0 .. 3). The device has memory blocks each containing one of the subarrays, a word decoder (WDO .. 3) and column decoder (CDO .. 3). Each of the memory blocks (MC) is selected independently to perform an access operation and refresh operation. As long as different memory blocks (MC) are selected for respective operations, the both operations are performed in paralle, however when the same memory block (MC) is selected for both operations, namely double selected, a comparison circuit (43) detects the double selection and the priority to one of both operations are determined and perform the operation selected preferentially. Usually, the refresh oriented operation is allowed. However, in order to decrease 'busy ratio' of the device, the refresh access operations is performed preferentially. Further complicated operation for priority selection, is performed according to a predetermined schedule memorized in a priority providing means (46, 48). In addition, a common word bus line (CWLi) is proposed for accessing each memory blocks, namely each sub-arrays, in order to reduce common word lines for realizing a further high packing density of the DRAM device. This common bus line is also applicable to other device such as a static RAM.

    Semiconductor memory device with shift registers for high speed reading and writing
    59.
    发明公开
    Semiconductor memory device with shift registers for high speed reading and writing 失效
    具有用于高速读取和写入的移位寄存器的半导体存储器件

    公开(公告)号：EP0182719A3

    公开(公告)日：1988-08-03

    申请号：EP85402246

    申请日：1985-11-20

    申请人： FUJITSU LIMITED

    发明人： Ogawa, Junji ,  Takemae, Yoshihiro

    IPC分类号： G11C07/00

    CPC分类号： G11C7/1075

    摘要： 57 A semiconductor memory device with shift registers used for a video RAM (1), including a memory cell array, bit lines (BL, BL), and word lines (WL), a pair of shift registers (3, 4), and transfer gate circuits (21,22) arranged between the bit lines and the shift registers. Each parallel data transfer circuit is provided between the shift registers for the parallel data transfer between the shift registers, so that high-speed reading and writing of data for a CRT display is realized.

    Semiconductor memory device
    60.
    发明公开
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：EP0143647A3

    公开(公告)日：1988-03-16

    申请号：EP84308237

    申请日：1984-11-28

    申请人： FUJITSU LIMITED

    发明人： Takemae, Yoshihiro ,  Nakano, Tomio Shirakatadai-jutaku 12-404 ,  Nakano, Masao ,  Sato, Kimiaki

    IPC分类号： G11C08/00

    CPC分类号： G11C8/04 ,  G11C7/1024 ,  G11C7/1033 ,  G11C8/18

    摘要： A semiconductor memory device having an operational mode such as a nibble mode or page mode, wherein, with a first address strobe signal (RAS) kept in an active state, a second address strobe signal (CAS) is successively switched between an active state and standby state, thereby enabling successive data output (Dout). Previous data output is once reset in accordance with the switchover of the second address strobe signal to the active state while the first address strobe signal is in the active state, before data output is performed, and the reset operation of the data output is also performed when both the first and second address strobe signals are switched to the standby state, so that the period of the output data can be expanded.

    摘要翻译： 一种具有诸如半字节模式或页面模式的操作模式的半导体存储器件，其中，在第一地址选通信号（RAS）保持在激活状态的情况下，第二地址选通信号（CAS）在激活状态和 待机状态，从而启用连续的数据输出（Dout）。 在第一地址选通信号处于激活状态时，在执行数据输出之前，先前的数据输出根据第二地址选通信号切换到激活状态而被复位，并且还执行数据输出的复位操作 当第一和第二地址选通信号都被切换到待机状态时，使得输出数据的周期可以被扩展。