公开(公告)号：EP1369926A2

公开(公告)日：2003-12-10

申请号：EP03253199.8

申请日：2003-05-22

申请人： SHARP KABUSHIKI KAISHA

发明人： Hsu, Sheng Teng ,  Zhang, Fengyan ,  Li, Tingkai

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L21/8246

CPC分类号： G11C11/22 ,  H01L21/28291 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L27/11502 ,  H01L29/78391

摘要： An object of the present invention is to provide a non-volatile ferroelectric memory device, which eliminates leakage-related transistor memory retention degradation. A ferroelectric memory transistor according to the present invention comprises: a substrate having a source region (54), a gate region (58), and a drain region (56); a gate stack (60) located on the gate region, including: a high-k insulator element (62), including a first high-k cup (62L) and a second high-k cup (62U); a ferroelectric element (64), wherein said ferroelectric element is encapsulated within said high-k insulator element (62); and a top electrode (66) located on a top portion of said high-k insulator element; a passivation oxide layer (68) located over the substrate and gate stack; and metalizations (70,74,72) to form respective contacts to the source region, the drain region and the gate stack.

摘要翻译： 本发明的目的是提供一种消除漏电相关晶体管存储器保持性降低的非挥发性铁电存储器件。 根据本发明的铁电存储晶体管包括：具有源极区（54），栅极区（58）和漏极区（56）的衬底; 位于所述栅极区域上的栅叠层（60）包括：高k绝缘体元件（62），包括第一高k杯（62L）和第二高k杯（62U）; 铁电元件（64），其中所述铁电元件被封装在所述高k绝缘体元件（62）内; 以及位于所述高k绝缘体元件的顶部上的顶部电极（66） 钝化氧化物层（68），其位于所述衬底和栅极堆叠之上; 和金属化（70,74,72）以形成到源极区域，漏极区域和栅极叠层的相应触点。

公开(公告)号：EP1345259A2

公开(公告)日：2003-09-17

申请号：EP03251457.2

申请日：2003-03-11

申请人： Sharp Kabushiki Kaisha

发明人： Hsu, Sheng Teng ,  Li, Tingkai ,  Zhuang, Wei-Wei

IPC分类号： H01L21/02 ,  G11C11/00 ,  H01L21/28

CPC分类号： H01L28/56 ,  G11C13/0007 ,  G11C2213/31 ,  H01L21/28291 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

摘要： The invention provides a polycrystalline memory structure comprising: a polycrystalline memory layer (18) overlying a substrate (14) and having crystal grain boundaries forming gaps (20) between adjacent crystallites; and an insulating material (24) at least partially within the gaps.

摘要翻译： 本发明提供的多晶存储器结构，包括：存储器的多晶层（18）覆盖衬底（14）和具有在相邻的晶体吸住之间的间隙（20）的晶界; 和部分内的间隙的绝缘至少材料（24）的。

公开(公告)号：EP1291881A2

公开(公告)日：2003-03-12

申请号：EP02256128.6

申请日：2002-09-04

申请人： SHARP KABUSHIKI KAISHA

发明人： Hsu, Sheng Teng

IPC分类号： G11C11/56

CPC分类号： G11C13/004 ,  G11C7/06 ,  G11C11/56 ,  G11C11/5642

摘要： A read circuit for a multibit memory cell is provided to convert a multi-level voltage output from the multibit memory cell into the desired number of binary levels. For example, if the multibit memory cell can be programmed to have four resistance levels, which produce four output voltages respectively, the read circuit is provided with two binary outputs. For additional resistance levels, and corresponding voltage levels, additional binary outputs may be provided.

摘要翻译： 提供用于多位存储器单元的读取电路以将从多位存储器单元输出的多电平电压转换为期望数量的二进制电平。 例如，如果多位存储单元可被编程为具有分别产生四个输出电压的四个电阻电平，则读取电路具有两个二进制输出。 对于额外的电阻电平和相应的电压电平，可以提供额外的二进制输出。

公开(公告)号：EP1049148A3

公开(公告)日：2002-05-29

申请号：EP00303640.7

申请日：2000-04-28

申请人： SHARP KABUSHIKI KAISHA

发明人： Li, Tingkai ,  Zhang, Fengyan ,  Ono, Yoshi ,  Hsu, Sheng Teng

IPC分类号： C23C16/40 ,  H01L21/316

CPC分类号： H01L21/31691 ,  C23C16/40 ,  H01L21/31604 ,  Y10S438/933 ,  Y10T428/12674 ,  Y10T428/12701 ,  Y10T428/12875

摘要： A ferroelectric Pb 5 Ge 3 O 11 (PGO) thin film is provided with a metal organic vapor deposition (MOCVD) process and RTP (Rapid Thermal Process) annealing techniques. The PGO film is substantially crystallization with c-axis orientation at temperature between 450 and 650° C. The PGO film has an average grain size of about 0.5 microns, with a deviation in grain size uniformity of less than 10%. Good ferroelectric properties are obtained for a 150 nm thick film with Ir electrodes. The films also show fatigue-free characteristics: no fatigue was observed up to 1 x 10 8 switching cycles. The leakage currents increase with increasing applied voltage, and are about 3.6 x10 -7 A/cm 2 at 100 kV/cm. The dielectric constant shows a behavior similar to most ferroelectric materials, with a maximum dielectric constant of about 45. These high quality MOCVD Pb 5 Ge 3 O 11 films can be used for high density single transistor ferroelectric memory applications because of the homogeneity of the PGO film grain size.

公开(公告)号：EP1049147A3

公开(公告)日：2002-05-29

申请号：EP00303598.7

申请日：2000-04-28

申请人： SHARP KABUSHIKI KAISHA

发明人： Li, Tingkai ,  Zhang, Fengyan ,  Ono, Yoshi ,  Hsu, Sheng Teng

IPC分类号： C23C16/40 ,  H01L21/316 ,  C30B25/02

CPC分类号： H01L21/31604 ,  C23C16/40 ,  H01L21/31691 ,  Y10S438/933

摘要： The present invention provides a substantially single crystal PGO film with optimal the ferroelectric properties. The PGO film and adjacent electrodes are epitaxially grown to minimize mismatch between the structures. MOCVD deposition methods and RTP annealing procedures permit a PGO film to be epitaxially grown in commercial fabrication processes. These epitaxial ferroelectric have application in FeRAM memory devices. The present invention deposition method epitaxially grows ferroelectric Pb 5 Ge 3 O 11 thin films along with c-axis orientation.

公开(公告)号：EP1035588A3

公开(公告)日：2002-03-20

申请号：EP00301789.4

申请日：2000-03-06

申请人： SHARP KABUSHIKI KAISHA ,  Sharp Laboratories of America, Inc.

发明人： Zhang, Fengyan ,  Maa, Jer-Shen ,  Hsu, Sheng Teng

IPC分类号： H01L29/45 ,  H01L21/28

CPC分类号： H01L29/456 ,  H01L21/28291 ,  H01L28/55 ,  H01L28/65

摘要： A conductive barrier, useful as a ferroelectric capacitor electrode, having high temperature stability has been provided. This conductive barrier permits the use of iridium (Ir) metal in IC processes involving annealing. Separating silicon substrate from Ir film with an intervening, adjacent, tantalum (Ta) film has been found to very effective in suppressing diffusion between layers. The Ir prevents the interdiffusion of oxygen into the silicon during annealing. A Ta or TaN layer prevents the diffusion of Ir into the silicon. This Ir/TaN structure protects the silicon interface so that adhesion, conductance, hillock, and peeling problems are minimized. The use of Ti overlying the Ir/TaN structure also helps prevent hillock formation during annealing. A method of forming a multilayer Ir conductive structure and Ir ferroelectric electrode are also provided.

摘要翻译： 已经提供了具有高温稳定性的用作铁电电容器电极的导电屏障。 该导电屏障允许在涉及退火的IC工艺中使用铱（Ir）金属。 已经发现将硅衬底与Ir膜分隔开，其间隔相邻的钽（Ta）膜在抑制层之间的扩散方面非常有效。 Ir防止退火过程中氧进入硅的相互扩散。 Ta或TaN层防止Ir扩散到硅中。 这种Ir / TaN结构保护了硅界面，使得粘附，电导，小丘和剥离问题最小化。 使用覆盖Ir / TaN结构的Ti也有助于防止退火过程中的小丘形成。 还提供了形成多层Ir导电结构和Ir铁电电极的方法。

公开(公告)号：EP1184485A1

公开(公告)日：2002-03-06

申请号：EP01307249.1

申请日：2001-08-24

申请人： SHARP KABUSHIKI KAISHA

发明人： Li, Tingkai ,  Zhuang, Wei-Wei ,  Hsu, Sheng Teng

IPC分类号： C23C16/40

CPC分类号： C23C16/40 ,  C23C16/409

摘要： A ferroelectric and dielectric source solution for use in chemical vapor deposition includes a ferroelectric/dielectric chemical vapor deposition precursor, and a solvent for the ferroelectric/dielectric chemical vapor deposition precursor selected from type A solvents including tetraglyme, triglyme, triethylenetetramine, N,N,N',N'-tetramethylethylenediamine, N,N,N',N',N",N"-pentamethyldiethylenetriamine, and 2,2'-bipyridine; type B solvents including tetrahydrofuran, butyl ethyl ether, tert-butyl ethyl ether, butyl ether and pentyl ether; type C solvents including iso-propanol, 2-butanol, 2-ethyl-1-hexanol, 2-pentanol, toluene, xylene and butyl acetate; and mixtures of types A, B and C solvents.

摘要翻译： 用于化学气相沉积的铁电和电介质源溶液包括铁电/电介质化学气相沉积前体，以及选自A型溶剂的铁电/电介质化学气相沉积前体的溶剂，包括四甘醇二甲醚，三甘醇二甲醚，三亚乙基四胺，N，N， N'，N'-四甲基乙二胺，N，N，N'，N'，N“，N” - 五甲基二亚乙基三胺和2,2'-联吡啶; B型溶剂，包括四氢呋喃，丁基乙基醚，叔丁基乙基醚，丁基醚和戊基醚; C型溶剂包括异丙醇，2-丁醇，2-乙基-1-己醇，2-戊醇，甲苯，二甲苯和乙酸丁酯; 以及A，B和C类溶剂的混合物。

公开(公告)号：EP1122771A3

公开(公告)日：2001-11-28

申请号：EP01300938.6

申请日：2001-02-02

申请人： SHARP KABUSHIKI KAISHA

发明人： Sakiyama, Keizo ,  Hsu, Sheng Teng

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/417 ,  H01L29/45

CPC分类号： H01L29/66772 ,  H01L21/76895 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66575 ,  H01L29/78618 ,  H01L29/78654

摘要： A method is provided for forming silicided source/drain electrodes in active devices in which the electrodes have very thin junction regions. In the process, adjacent active areas are separated by isolation regions, typically by LOCOS isolation, trench isolation or SOI/SIMOX isolation. A contact material, preferably silicide, is deposited over the wafer and the underling structures, including gate and interconnect electrodes. The silicide is then planed away using CMP, or another suitable planing process, to a height approximate the height of the highest structure. The silicide is then electrically isolated from the electrodes, using an etch back process, or other suitable process, to lower the silicide to a height below the height of the gate or interconnect electrode. The wafer is then patterned and etched to remove unwanted silicide. The remaining silicide typically forms silicided source regions and silicided drain regions that extend over a portion of the adjacent isolation regions such that the silicided source/drain regions are larger than the underlying source/drain regions to provide a larger contact area.

公开(公告)号：EP1073109A2

公开(公告)日：2001-01-31

申请号：EP00306349.2

申请日：2000-07-26

申请人： SHARP KABUSHIKI KAISHA

发明人： Li, Tingkai ,  Zhang, Fengyan ,  Hsu, Sheng Teng

IPC分类号： H01L21/316

CPC分类号： H01L28/55 ,  C23C16/409 ,  H01L21/31604 ,  H01L21/31691

摘要： A ferroelectric device is provided with a single phase, high quality, ferroelectric film orientationally grown on a Pt electrode. The Pt electrode is orientationally grown on a material that has the lattice structure desired in the ferroelectric film. The Pt electrode adopts the lattice structure of the underlying layer, so that lattice mismatch between the Pt and the ferroelectric film is minimized. This adjustment in the Pt lattice structure permits the formation of single phase perovskite ferroelectric films, on Pt electrodes, at low deposition temperatures. As a result, ferroelectric devices with low leakage current, and completely saturated, square, symmetrical hysteresis loops are formed. A method of forming the ferroelectric film, of the above-mentioned ferroelectric device, is also provided.

摘要翻译： 铁电体器件设置有在Pt电极上取向生长的单相，高质量的铁电体膜。 Pt电极在铁电体膜中具有所需晶格结构的材料上取向生长。 Pt电极采用下层的晶格结构，使Pt和铁电体膜之间的晶格失配最小化。 Pt晶格结构中的这种调整允许在Pt电极上在低沉积温度下形成单相钙钛矿铁电薄膜。 结果，形成具有低漏电流和完全饱和，正方形，对称的磁滞回线的铁电器件。 还提供了上述铁电体元件形成铁电体膜的方法。

公开(公告)号：EP1049149A2

公开(公告)日：2000-11-02

申请号：EP00303641.5

申请日：2000-04-28

申请人： SHARP KABUSHIKI KAISHA

发明人： Li, Tingkai ,  Zhang, Fengyan ,  Hsu, Sheng Teng

IPC分类号： H01L21/316

CPC分类号： H01L21/31691 ,  C23C16/40 ,  H01L21/31604 ,  H01L28/55

摘要： A MOCVD deposition process has been provided for the deposition of an improved PGO ferroelectric film. The inclusion of a second phase of Pb 3 GeO 5 , along with the first phase of Pb 5 Ge 3 O 11 , provides the film with some ferroelastic properties which direct correspond to improved ferroelectric characteristics. The inclusion of the second phase regulates to first phase crystal grain size and promotes the preferred c-axis orientation of the grains. The degree of second phase Pb 3 GeO 5 is regulated by controlling the amount of lead in the precursor, and with additional lead added to the reactor along the oxygen used to oxidize the lead-germanium film. Critical post-deposition annealing process are also described which optimize the ferroelectric properties of the PGO film. A multi-phase PGO film and capacitor structure including multi-phase PGO film of the present invention are also provided.

摘要翻译： 已经提供了用于沉积改进的PGO铁电体膜的MOCVD沉积工艺。 包含Pb3GeO5的第二相以及Pb5Ge3O11的第一相为膜提供一些直接对应于改进的铁电特性的铁弹性质。 包含第二相调节到第一相晶粒尺寸并促进晶粒的优选的c轴取向。 第二相Pb3GeO5的程度通过控制前体中的铅的量来调节，并且另外的铅沿着用于氧化铅 - 锗膜的氧气添加到反应器中。 还描述了优化PGO膜的铁电性能的关键后沉积退火工艺。 还提供了包括本发明的多相PGO膜的多相PGO膜和电容器结构。