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公开(公告)号：EP2102869A4
公开(公告)日：2009-12-30
申请号：EP07845609
申请日：2007-11-29
发明人： PYEON HONG BEOM
CPC分类号： G11C29/32 , G11C29/003 , G11C29/40 , G11C2029/0409 , G11C2029/2602
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52.发明公开Compression of data traces for an integrated circuit with multiple memories 有权Datenspurkomprimierungfüreine integrierte Schaltung mit mehreren Speichern
公开(公告)号：EP2012324A1
公开(公告)日：2009-01-07
申请号：EP08165088.9
申请日：2005-05-11
发明人： JOHN, Johnny K.
IPC分类号： G11C29/00 , G01R31/3185
CPC分类号： G06F11/348 , G01R31/3177 , G01R31/318505 , G06F11/3471 , G06F11/3476 , G11C29/40 , G11C29/56008 , G11C2029/0401
摘要： Techniques for performing data tracing in an integrated circuit with multiple embedded memories are described. A trace module within the integrated circuit forms packets of trace data for memory accesses of the multiple memories. The trace module includes multiple data capture units (one for each memory) and a trace stream generator. Each data capture unit includes a register, a comparator, an address compressor, a data compressor, and a packetizer. The register stores an address for a prior memory access of the associated memory. The comparator compares an address for a current memory access against the address stored in the register. The address and data compressors perform address and data compression, respectively, for the current memory access. The packetizer forms a packet of trace data for the current memory access. The trace stream generator generates a stream containing trace data packets from all data capture units.
摘要翻译： 描述了在具有多个嵌入存储器的集成电路中执行数据跟踪的技术。 集成电路内的跟踪模块形成用于多个存储器的存储器访问的跟踪数据分组。 跟踪模块包括多个数据捕获单元（每个存储器一个）和跟踪流生成器。 每个数据捕获单元包括寄存器，比较器，地址压缩器，数据压缩器和打包器。 寄存器存储相关存储器的先前存储器访问的地址。 比较器将当前存储器访问的地址与存储在寄存器中的地址进行比较。 地址和数据压缩器分别对当前存储器访问执行地址和数据压缩。 打包器形成用于当前存储器访问的跟踪数据的分组。 跟踪流生成器生成包含来自所有数据捕获单元的跟踪数据包的流。
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53.发明授权Memory test method and nonvolatile memory with low error masking probability 有权存储器的测试方法和错误隐藏的非易失性存储器中，术语低概率
公开(公告)号：EP1089293B1
公开(公告)日：2008-12-10
申请号：EP99830617.9
申请日：1999-09-30
发明人： Kumar, Promod
IPC分类号： G11C29/00
CPC分类号： G11C29/40
摘要： A nonvolatile memory device (10) has a signature code generator (14, 15, 17) generating a present signature code (Q) from an algorithm modified dynamically as a function of predefined varying parameters. A variable parameter may be the address (A) of a memory cell being addressed; in this case the output of the code generator (Q) is a function of data (D) read from the cell array (24), the previously calculated signature code (Q) and the address of the read data. The data are read in sequence, using an internal clock (CK) generated by an internal clock oscillator (11). In test mode, the memory is scanned sequentially, beginning from any memory location, selected randomly, and the signature code (Q) varies in dynamic way; at the end of memory scanning, the signature code (Q) is compared to an expected result.
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54.发明授权
公开(公告)号：EP1745489B1
公开(公告)日：2008-10-01
申请号：EP05748092.3
申请日：2005-05-11
发明人： JOHN, Johnny K.
IPC分类号： G11C29/00 , G01R31/3185
CPC分类号： G06F11/348 , G01R31/3177 , G01R31/318505 , G06F11/3471 , G06F11/3476 , G11C29/40 , G11C29/56008 , G11C2029/0401
摘要： Techniques for performing data tracing in an integrated circuit with multiple embedded memories are described. A trace module within the integrated circuit forms packets of trace data for memory accesses of the multiple memories. The trace module includes multiple data capture units (one for each memory) and a trace stream generator. Each data capture unit includes a register, a comparator, an address compressor, a data compressor, and a packetizer. The register stores an address for a prior memory access of the associated memory. The comparator compares an address for a current memory access against the address stored in the register. The address and data compressors perform address and data compression, respectively, for the current memory access. The packetizer forms a packet of trace data for the current memory access. The trace stream generator generates a stream containing trace data packets from all data capture units.
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55.发明授权
公开(公告)号：EP1061526B1
公开(公告)日：2008-08-27
申请号：EP00106931.9
申请日：2000-03-31
申请人： Qimonda AG
发明人： Frankowsky, Gerd
IPC分类号： G11C29/00
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公开(公告)号：EP1389336B1
公开(公告)日：2007-04-11
申请号：EP02750932.2
申请日：2002-05-15
IPC分类号： G11C29/00
摘要： The invention relates to a method for testing a data memory with an integrated test data compression circuit (16). Said data memory (1) comprises a memory cell field (10) having a plurality of addressable memory cells, a write/read amplifier (12) for writing and reading data into the memory cells by means of an internal data bus (12) of the data memory (1), and a test data compression circuit (16). Test data sequences which are respectively successively read out of the memory cell field (10) are compressed with stored reference test data sequences in order to respectively produce a display date which indicates whether at least one data error has occurred in the test data sequence which has been read out.
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57.发明公开
公开(公告)号：EP1416641A1
公开(公告)日：2004-05-06
申请号：EP02425660.4
申请日：2002-10-30
发明人： Barone, Massimiliano
摘要： Described herein is a method for compressing a sequence of repetitive data, which uses in combination one or more words with a format for non-compressible data and one or more words with a format for compressible data, in which a word with a format for non-compressible data is made up of a set of bits, in which the most significant bit is set at the logic value "1" and the remaining bits are the bits of a non-compressible datum to be encoded, whilst a word with a format for compressible data is made up of a set of bits, in which the most significant bit is set at a the logic value "0", the next five most significant bits indicate the total number of subsequent words which encode the sequence of repetitive data, and the remaining eleven bits indicate the number of times that the words indicated by the preceding five most significant bits are repeated.
摘要翻译： 使用非可压缩和可压缩数据的组合对重复数据的序列进行编码。 非压缩数据的最高有效位（MSB）设置为逻辑1'，而其余位是数据位。 压缩数据的MSB设置为逻辑值0'。 接下来的五个MSB显示编码重复数据所需的单词总数，而剩余的位表示重复次数。
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公开(公告)号：EP1389336A1
公开(公告)日：2004-02-18
申请号：EP02750932.2
申请日：2002-05-15
IPC分类号： G11C29/00
摘要： The invention relates to a method for testing a data memory with an integrated test data compression circuit (16). Said data memory (1) comprises a memory cell field (10) having a plurality of addressable memory cells, a write/read amplifier (12) for writing and reading data into the memory cells by means of an internal data bus (12) of the data memory (1), and a test data compression circuit (16). Test data sequences which are respectively successively read out of the memory cell field (10) are compressed with stored reference test data sequences in order to respectively produce a display date which indicates whether at least one data error has occurred in the test data sequence which has been read out.
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60.发明公开Memory test method and nonvolatile memory with low error masking probability 有权存储器的测试方法和错误隐藏的非易失性存储器中，术语低概率
公开(公告)号：EP1089293A1
公开(公告)日：2001-04-04
申请号：EP99830617.9
申请日：1999-09-30
发明人： Kumar, Promod
IPC分类号： G11C29/00
CPC分类号： G11C29/40
摘要： A nonvolatile memory device (10) has a signature code generator (14, 15, 17) generating a present signature code (Q) from an algorithm modified dynamically as a function of predefined varying parameters. A variable parameter may be the address (A) of a memory cell being addressed; in this case the output of the code generator (Q) is a function of data (D) read from the cell array (24), the previously calculated signature code (Q) and the address of the read data. The data are read in sequence, using an internal clock (CK) generated by an internal clock oscillator (11). In test mode, the memory is scanned sequentially, beginning from any memory location, selected randomly, and the signature code (Q) varies in dynamic way; at the end of memory scanning, the signature code (Q) is compared to an expected result.
摘要翻译： 一种非易失性存储器装置（10）有一个签名码发生器（14，15，17）生成从在算法动态地修改为预定义的参数变化的函数的本签名代码（Q）。 可变参数可以是被寻址的存储器单元的地址（A）; 在这种情况下，代码生成器（Q）的输出是从单元阵列（24）读取的数据（D）的函数，所述先前计算的签名代码（Q）和所述数据的地址读出。 数据被依次读出，利用在通过在内部时钟振荡器（11）产生的内部时钟（CK）。 在测试模式中，所述存储器被顺序扫描，从任何存储器位置处开始，随机选择的，并且签名代码（Q）变化在动态的方式; 在存储器扫描结束，签名代码（Q）预计将导致相比。
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