公开(公告)号：EP3510596A1

公开(公告)日：2019-07-17

申请号：EP17755399.7

申请日：2017-08-11

申请人： Qualcomm Incorporated

发明人： LIANG, Bin ,  KWOK, Tony Chung Yiu ,  LI, Rui ,  YOON, Sei Seung

IPC分类号： G11C7/22 ,  G11C8/18 ,  G11C11/418 ,  G11C11/419

摘要： A memory is disclosed. The memory includes a memory array having a plurality of memory cells. The memory also includes an address decoder configured to assert a wordline to enable the memory cells. Additionally, the memory includes a tracking circuit configured to vary a duration of asserting the wordline as a function of which one of the memory cells is accessed. A method is also disclosed. The method includes asserting a wordline to enable the memory cells and varying a duration of asserting the wordline as a function of which one of a plurality of memory cells is accessed.

公开(公告)号：EP3424050A1

公开(公告)日：2019-01-09

申请号：EP17710365.2

申请日：2017-02-27

申请人： Surecore Limited

发明人： COSEMANS, Stefan

IPC分类号： G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C11/419 ,  G11C11/418

摘要： There is provided a multiple data rate memory comprising a clock splitting circuit and a multiplexing address latch. The clock splitting circuit is configured to generate first and second internal clock pulses from a rising edge of an external clock signal and to provide the first and second internal clock signals to the multiplexing address latch. The multiplexing address latch is configured to output a first address signal in response to the first internal clock pulse and a second address signal in response to the second internal clock pulse.

公开(公告)号：EP3197051A1

公开(公告)日：2017-07-26

申请号：EP16200527.6

申请日：2016-11-24

申请人： eMemory Technology Inc.

发明人： Po, Chen-Hao

IPC分类号： H03K3/356 ,  G11C16/10 ,  H01L23/528 ,  G11C7/12 ,  G11C8/18

摘要： A driving circuit includes a driving stage with a first level shifter and a second level shifter. The first level shifter includes an input terminal receiving a first control signal, an inverted input terminal receiving an inverted first control signal, a first output terminal, and a second output terminal. The second level shifter includes an input terminal receiving a second control signal, an inverted input terminal receiving an inverted second control signal, a third output terminal, and a fourth output terminal. The first output terminal and the third output terminal are connected with each other to generate an output signal. The second output terminal and the fourth output terminal are connected with each other to generate an inverted output signal. Moreover, only one of the first level shifter and the second level shifter is enabled according to an operation mode of the driving circuit.

摘要翻译： 驱动电路包括具有第一电平移位器和第二电平移位器的驱动级。 第一电平移位器包括接收第一控制信号的输入端子，接收反相的第一控制信号的反相输入端子，第一输出端子和第二输出端子。 第二电平移位器包括接收第二控制信号的输入端子，接收反相的第二控制信号的反相输入端子，第三输出端子和第四输出端子。 第一输出端子和第三输出端子彼此连接以产生输出信号。 第二输出端子和第四输出端子彼此连接以产生反相输出信号。 而且，根据驱动电路的操作模式，第一电平移位器和第二电平移位器中仅有一个被使能。

公开(公告)号：EP1269473B1

公开(公告)日：2014-06-11

申请号：EP01924470.6

申请日：2001-03-30

申请人： Round Rock Research, LLC

发明人： ROOHPARVAR, Frankie, F.

IPC分类号： G11C8/18 ,  G06F13/16 ,  G11C16/10 ,  G11C16/26

CPC分类号： G11C7/106 ,  G06F13/1615 ,  G06F13/1668 ,  G06F13/1694 ,  G06F13/4243 ,  G11C7/10 ,  G11C7/1015 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/18 ,  G11C16/10 ,  G11C16/26 ,  G11C2207/105 ,  G11C2207/2281 ,  G11C2207/229 ,  G11C2216/22

公开(公告)号：EP2672485A2

公开(公告)日：2013-12-11

申请号：EP13169562.9

申请日：2013-05-28

申请人： Freescale Semiconductor, Inc.

发明人： Ramamurthy, Hema ,  Ramaraju , Ravindraraj

IPC分类号： G11C7/22 ,  G11C8/08 ,  G11C8/18

CPC分类号： G11C8/10 ,  G11C7/222 ,  G11C8/08 ,  G11C8/18

摘要： A memory (10) includes a memory array (12) having a plurality of word lines (WL), a plurality of latching predecoders (18), and word line driver logic (14). Each latching predecoder receives a clock signal (CLK) and a plurality of address signals (A0, A0b) and latches a result of a logic function of the plurality of address signals in response to a first edge of a clock cycle of the clock signal and provides a predetermined value in response to a second edge of the first clock cycle of the clock signal, wherein, in response to the second edge, every latching decoder of the plurality of latching predecoders provides a same predetermined value. The word line driver logic selectively activates a selected word line of the plurality of word lines in response to the latched results.

摘要翻译： 存储器（10）包括具有多个字线（WL），多个锁存预解码器（18）和字线驱动器逻辑（14）的存储器阵列（12）。 每个锁存预解码器响应于时钟信号的时钟周期的第一个边缘接收时钟信号（CLK）和多个地址信号（A0，A0b）并锁存多个地址信号的逻辑功能的结果， 提供响应于时钟信号的第一时钟周期的第二边缘的预定值，其中响应于第二边缘，多个锁存预解码器中的每个锁存解码器提供相同的预定值。 字线驱动器逻辑响应于锁存结果选择性地激活多个字线中的选定字线。

公开(公告)号：EP1301927B1

公开(公告)日：2012-06-27

申请号：EP01951275.5

申请日：2001-07-06

申请人： Mosaid Technologies Incorporated

发明人： DEMONE, Paul

IPC分类号： G11C11/408 ,  G11C11/4076 ,  G11C7/22 ,  G11C8/18

CPC分类号： G11C7/1072 ,  G11C7/08 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091 ,  G11C2207/002 ,  G11C2207/065 ,  G11C2207/2281

摘要： A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit lines pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line timing pulse by a first predetermined period, a first logic circuit for logically combining the word line timing pulse and the delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit, a second delay circuit for delaying the word line timing pulse by a second predetermined period, and a second logic circuit for logically combining the word line timing pulse and the second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein the second predetermined time period is selected so that ones of a plurality of column access devices are activated after the sense amplifier power supply circuit is enabled.

公开(公告)号：EP2428960A1

公开(公告)日：2012-03-14

申请号：EP11009644.3

申请日：2008-02-05

申请人： MOSAID Technologies Incorporated

发明人： Oh, HakJune

IPC分类号： G11C8/18 ,  G06F1/10 ,  G11C19/00 ,  G11C8/12 ,  H03L7/081

CPC分类号： G11C19/00 ,  G06F1/10 ,  H03L7/0812

摘要： A system includes a system controller (102) and a configuration of series-connected semiconductor devices (104). Such a device includes an input for receiving a clock signal originating from a previous device, and an output for providing a synchronized clock signal destined for a succeeding device. The device further includes a clock synchronizer (110) for producing the synchronized clock signal by processing the received clock signal and an earlier version of the synchronized clock signal. The device further includes a device controller for adjusting a parameter used by the clock synchronizer in processing the earlier version of the synchronized clock signal. The system controller further includes a detector (506) for processing the first and second clock signals (S TCK ,S RCK ) to detect a phase difference therebetween; and a synchronization controller (508) for commanding an adjustment to the clock synchronizer in at least one of the devices based on the phase difference (S DIFF ) detected by the detector.

摘要翻译： 一种系统，包括系统控制器（102）和串联连接的半导体器件（104）的配置。 这样的装置包括用于接收时钟信号源自从以前装置，以及输出，用于提供去往后续装置的同步时钟信号输入端。 该设备包括用于通过处理接收的时钟信号和同步时钟信号的早期版本产生所述同步时钟信号的时钟同步。此外（110）。 该装置包括用于调节在处理同步时钟信号的早期版本所使用的时钟同步的参数的进一步的设备控制器。 该系统控制器还包括用于处理所述第一和第二时钟信号（TCK S，S RCK），以有检测之间的相位差的检测器（506）; 及用于基于所述相位差的装置的至少一个指令，以调整到时钟同步的同步控制器（508）（S DIFF）由检测器检测。

公开(公告)号：EP2118902A4

公开(公告)日：2010-11-24

申请号：EP08714560

申请日：2008-02-05

申请人： MOSAID TECHNOLOGIES INC

发明人： OH HAKJUNE

IPC分类号： G11C8/18 ,  G06F1/10 ,  G11C8/12 ,  G11C19/00 ,  H03L7/081

CPC分类号： G11C19/00 ,  G06F1/10 ,  H03L7/0812

公开(公告)号：EP2097902A1

公开(公告)日：2009-09-09

申请号：EP07855465.6

申请日：2007-12-04

申请人： Mosaid Technologies Incorporated

发明人： PYEON, Hong Beom ,  OH, HakJune

IPC分类号： G11C7/10 ,  G06F1/04 ,  G06F12/00 ,  G11C19/00 ,  G11C7/22 ,  G11C8/18 ,  H03M9/00

CPC分类号： G11C5/066 ,  G06F13/1673 ,  G06F13/28 ,  G11C7/10 ,  G11C7/1078 ,  G11C7/1093 ,  G11C2207/107

摘要： A serial input processing apparatus provides how to capture serial data without loss of a single bit while command interpretation is being performed in a command decoder at high frequency. Individual bytes of serial bits of a pre-defined sequence are latched and bit streams are temporarily stored with multiple clocks. The temporary store is conducted before transferring byte information to assigned address registers to register the address. The address registration and the data registration are performed by latching all bit streams of the serial input at the leading edges of clocks. While at a high frequency operation (e.g., 1 GHz or 1 ns cycle time), no additional registers are required for storing bit data during command interpretation with enough time margins between the command bit stream interpretation and next bit data stream.

公开(公告)号：EP1690260A1

公开(公告)日：2006-08-16

申请号：EP04808855.3

申请日：2004-11-24

申请人： Thin Film Electronics ASA

发明人： HAMBERG, Per ,  KARLSSON, Christer ,  NORDAL, Per-Erik ,  OJAKANGAS, Nicklas ,  CARLSSON, Johan ,  GUDESEN, Hans, Gude

IPC分类号： G11C8/06 ,  G11C8/18 ,  G11C11/22

CPC分类号： G11C11/22 ,  G06F12/0238 ,  G06F2212/1036 ,  G06F2212/7211 ,  G11C8/12 ,  G11C2013/0083

摘要： In a method for reducing detrimental phenomena related to disturb voltages in a data storage apparatus employing passive matrix addressing, particularly a memory device or a sensor device, an application of electric potentials conforming to an addressing operation is generally controlled in a time-coordinated manner according to a voltage pulse protocol. In an addressing operation a data storage cell is set to a first polarization state by means of a first active voltage pulse and then, dependent on the voltage pulse protocol, a second voltage pulse which may be a second active voltage pulse of opposite polarity to that of the first voltage pulse, is applied and used for switching the data storage cell to a second polarization state. The addressed cell is thus set to a predetermined polarization state as specified by the addressing operation. The data storage cells of the apparatus are provided in two or more electrically separated segments such that each segment comprises a separate physical address space for the apparatus. In an addressing operation the data are directed to a segment that is selected based on information on prior and/or scheduled applications of active voltage pulses to the segments.