利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

142 条记录 (耗时 0.017 秒)

    Semiconductor memory device
    64.
    发明公开
    Semiconductor memory device 审中-公开
    一种半导体存储器件

    公开(公告)号：EP1796102A3

    公开(公告)日：2007-12-05

    申请号：EP06023247.7

    申请日：2006-11-08

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Ohsawa, Takashi

    IPC分类号： G11C11/406 ,  G11C11/408 ,  G11C11/4091 ,  H01L27/108 ,  H01L29/78

    CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C11/408 ,  G11C11/4091 ,  G11C2211/4016 ,  H01L27/10802 ,  H01L27/10897 ,  H01L29/7841

    摘要： The disclosure concerns a semiconductor memory device includes a memory cell array including memory cells; word lines; bit lines; a counter cell array including counter cells provided corresponding to the word lines and storing the number of times of activating the word lines; an adder incrementing the number of times of activating the word lines which is read out from the counter cell array, when data is read or written in the memory cell; a counter buffer circuit temporarily storing the number of times of activating the word lines, and writing back the incremented number of times of activating the word lines into the counter cell array; and a sense amplifier executing a refresh operation during a data read cycle or a data write cycle, when the number of times of activating one of the word lines has reached a predetermined value.

    Semiconductor memory device and manufacturing method thereof
    66.
    发明公开
    Semiconductor memory device and manufacturing method thereof 审中-公开
    Halbleiterspeichervorrichtung und Herstellungsverfahrendafür

    公开(公告)号：EP1826819A2

    公开(公告)日：2007-08-29

    申请号：EP07004031.6

    申请日：2007-02-27

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Shino, Tomoaki, c/o Toshiba Corporation

    IPC分类号： H01L27/12 ,  H01L21/84

    CPC分类号： H01L27/1203 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10897 ,  H01L27/1207 ,  H01L29/7841

    摘要： This disclosure concerns a semiconductor memory device comprising a supporting substrate including semiconductor materials; an insulation film provided above the supporting substrate; a first diffusion layer provided on the insulation film; a second diffusion layer provided on the insulation film; a body region provided between the first diffusion layer and the second diffusion layer, the body region being in an electrically floating state and accumulating or releasing electric charges for storing data; a semiconductor layer connected to the second diffusion layer to release electric charges from the second diffusion layer; a gate insulation film provided on the body region; and a gate electrode provided on the gate insulation film.

    摘要翻译： 本公开涉及一种半导体存储器件，包括：包括半导体材料的支撑衬底; 设置在所述支撑基板上方的绝缘膜; 设置在所述绝缘膜上的第一扩散层; 设置在所述绝缘膜上的第二扩散层; 身体区域，其设置在所述第一扩散层和所述第二扩散层之间，所述主体区域处于电浮动状态，并且累积或释放用于存储数据的电荷; 连接到所述第二扩散层以从所述第二扩散层释放电荷的半导体层; 设置在身体区域上的栅极绝缘膜; 以及设置在栅极绝缘膜上的栅电极。

    BIPOLAR READING TECHNIQUE FOR A MEMORY CELL HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR
    67.
    发明公开
    BIPOLAR READING TECHNIQUE FOR A MEMORY CELL HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR 审中-公开
    BIPOLAR读取技术用于与晶体管电浮体的存储单元

    公开(公告)号：EP1716600A1

    公开(公告)日：2006-11-02

    申请号：EP05850314.5

    申请日：2005-12-21

    申请人： Innovative Silicon SA

    发明人： OKHONIN, Serguei ,  NAGOGA, Mikhail

    IPC分类号： H01L29/78 ,  H01L27/108 ,  G11C11/404

    CPC分类号： G11C11/404 ,  G11C11/4076 ,  G11C2211/4016 ,  H01L27/1023 ,  H01L27/108 ,  H01L29/78 ,  H01L29/7841

    摘要： A technique of sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one embodiment, the present inventions are directed to a memory cell, having an electrically floating body transistor, and/or a technique of reading the data state in such a memory cell. In this regard, the present inventions employ the intrinsic bipolar transistor current to read and/or determine the data state of the electrically floating body memory cell (for example, whether the electrically floating body memory cell is programmed in a State '0' and State ''I'). During the read operation, the data state is determined primarily by or sensed substantially using the bipolar current responsive to the read control signals and significantly less by the interface channel current component, which is negligible relatively to the bipolar component. The bipolar transistor current may be very sensitive to the floating body potential due to the high gain of the intrinsic bipolar transistor. As such, the programming window obtainable with the bipolar reading technique may be considerably higher (for example, up two orders of magnitude higher) than the programming window employing a conventional reading technique (which is based primarily on the interface channel current component.

    SEMICONDUCTOR MEMORY CELL, ARRAY, ARCHITECTURE AND DEVICE, AND METHOD OF OPERATING SAME
    68.
    发明公开
    SEMICONDUCTOR MEMORY CELL, ARRAY, ARCHITECTURE AND DEVICE, AND METHOD OF OPERATING SAME 审中-公开
    半导体存储单元阵列，建筑以及设备和操作方法THEREFOR的

    公开(公告)号：EP1623432A2

    公开(公告)日：2006-02-08

    申请号：EP04751661.2

    申请日：2004-05-07

    申请人： Innovative Silicon, Inc. ,  ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)

    发明人： FERRANT, Richard ,  OKHONIN, Serguei ,  CARMAN, Eric ,  BRON, Michel

    IPC分类号： G11C16/04

    CPC分类号： G11C16/28 ,  G11C11/404 ,  G11C2211/4013 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

    摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of the invention, the memory cell (FIG. 3A, 3B) includes two transistors (102a, 102b) which store complementary data states (“0”, “1”). That is, the two-transistor memory cell includes a first transistor that maintains a complementary state relative to the second transistor. As such, when programmed, one of the transistors of the memory cell stores a logic low (a binary '0') and the other transistor of the memory cell stores a logic high (a binary “l”). The data state of the two-transistor complementary memory cell may be read and/or determined by sampling, sensing measuring and/or detecting the polarity of the logic states stored in each transistor of complementary memory cell (FIG. 4). That is, the two-transistor complementary memory cell is read by sampling, sensing measuring and/or detecting the difference in signals (current or voltage) stored in the two transistors.

    Semiconductor memory device and method of manufacturing the same
    69.
    发明公开
    Semiconductor memory device and method of manufacturing the same 审中-公开
    Halbleiter-Speicherbauteil und Verfahren zur Herstellung desselben

    公开(公告)号：EP1180799A3

    公开(公告)日：2005-09-28

    申请号：EP01119605.2

    申请日：2001-08-17

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Ohsawa, Takashi

    IPC分类号： H01L27/108 ,  H01L27/12 ,  G11C11/4076 ,  G11C11/406 ,  G11C11/404

    CPC分类号： H01L29/7841 ,  G11C7/02 ,  G11C7/18 ,  G11C11/404 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4097 ,  G11C2207/005 ,  G11C2207/2281 ,  G11C2207/229 ,  G11C2211/4016 ,  H01L21/84 ,  H01L21/845 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/1203 ,  H01L29/785

    摘要： A memory cell MC comprises one MOS transistor having a floating bulk region which is electrically isolated from others. A gate electrode 13 of the MOS transistor is connected to a word line WL, a drain diffusion region 14 thereof is connected to a bit line BL, and a source diffusion region 15 thereof is connected to a fixed potential line SL. The memory cell stores a first threshold state in which majority carriers produced by impact ionization are injected and held in the bulk region 12 of the MOS transistor and a second threshold state in which the majority carriers in the bulk region 12 of the MOS transistor are emitted by a forward bias at a pn junction on the drain side as binary data. Thereby, a semiconductor memory device in which a simple transistor structure is used as a memory cell, enabling dynamic storage of binary data by a small number of signal lines can be provided.

    摘要翻译： 存储单元MC包括具有与其它电气隔离的浮动块区的一个MOS晶体管。 MOS晶体管的栅电极13连接到字线WL，其漏极扩散区域14连接到位线BL，其源极扩散区域15连接到固定电位线SL。 存储单元存储第一阈值状态，其中通过冲击电离产生的多数载流子被注入并保持在MOS晶体管的体区域12中，并且第二阈值状态，其中MOS晶体管的体区12中的多数载流子被发射 通过在漏极侧的pn结处的正向偏压作为二进制数据。 因此，可以提供一种半导体存储器件，其中使用简单的晶体管结构作为存储单元，能够通过少量信号线实现二进制数据的动态存储。

    Semiconductor memory device
    70.
    发明公开
    Semiconductor memory device 审中-公开
    Halbleiter-Speicherbauteil

    公开(公告)号：EP1237193A2

    公开(公告)日：2002-09-04

    申请号：EP01121732.0

    申请日：2001-09-18

    申请人： Kabushiki Kaisha Toshiba

    发明人： Ohsawa, Takashi

    IPC分类号： H01L27/108 ,  H01L27/12

    CPC分类号： H01L27/10802 ,  G11C11/24 ,  G11C11/404 ,  H01L27/108 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/1203 ,  H01L29/7841

    摘要： A semiconductor memory device has MIS transistors to constitute a memory cell array. Each of the MIS transistors has a silicon layer (12) in a floating state. Furthermore, the MIS transistor has a second gate (20), a potential of which is fixed in order to control a potential of the silicon layer by a capacitive coupling, in addition to a first gate (13), which forms a channel between a source region and a drain region (14,15) of the MIS transistor. The MIS transistor dynamically stores a first data state in which the silicon layer has a first potential set by impact ionization generated near a drain junction (14) and a second data state in which the silicon layer has a second potential set by a forward current flowing through the drain junction.

    摘要翻译： 半导体存储器件具有构成存储单元阵列的MIS晶体管。 每个MIS晶体管具有处于浮置状态的硅层（12）。 此外，除了第一栅极（13）之外，MIS晶体管还具有第二栅极（20），第二栅极（20）的电位被固定以便通过电容耦合来控制硅层的电位，第一栅极（13） 源极区和漏极区（14,15）。 MIS晶体管动态地存储第一数据状态，其中硅层具有通过在漏极结（14）附近产生的冲击电离设置的第一电位和第二数据状态，其中硅层具有由正向电流流动设定的第二电位 通过漏极结。