公开(公告)号：EP2592757B1

公开(公告)日：2017-04-26

申请号：EP11189058.8

申请日：2011-11-14

Applicant: Telefonaktiebolaget LM Ericsson (publ)

Inventor： Sundström, Lars ,  Anderson, Martin

IPC: H03M3/00

CPC classification number: H03M3/422 ,  H03M3/374 ,  H03M3/454 ,  H03M3/464

Abstract: A continuous-time ”£-ADC (1) is disclosed, comprising a sampled quantizer (5) arranged to generate samples y(n) of a digital output signal of the ”£-ADC (1) at sample instants nT. The ”£-ADC (1) further comprises two or more DACs (10a-b), each arranged to generate an analog feedback signal based on the samples of the digital output signal generated by the sampled quantizer (5), and a continuous-time analog network (20) arranged to generate an analog input signal to the quantizer (5) based on the feedback signal(s) from the two or more DACs (10a-b) and an analog input signal to the 4E-ADC (1). At least a first DAC (10a) of the two or more DACs (10a-b) is adapted to generate a pulsed feedback signal that, for each n, comprises a pulse, the magnitude of which is proportional to the sample of the digital output signal at sample instant nT and which lasts between the time instants (n+±1)T and (n+²1)T, wherein 0

Abstract translation: 公开了一种连续时间“-ADC（1），包括被采样的量化器（5），被配置为在采样时刻nT产生”-ADC（1）的数字输出信号的采样y（n）“。 “-ADC（1）还包括两个或更多个DAC（10a-b），每个DAC（10a-b）被布置为基于由采样的量化器（5）生成的数字输出信号的采样来产生模拟反馈信号， 时间模拟网络（20），其被布置为基于来自所述两个或更多个DAC（10a-b）的反馈信号和到4E-ADC（1）的模拟输入信号，向量化器（5）生成模拟输入信号 ）。 两个或多个DAC（10a-b）中的至少第一DAC（10a）适于产生脉冲反馈信号，对于每个n，脉冲反馈信号包括脉冲，其幅度与数字输出的采样成比例 信号在采样时刻nT，并且在时刻（n +±1）T和（n + 21）T之间持续，其中0 <±1 <2 <1。两个或更多个DAC的至少第二DAC（10b） （10a-b）适于产生脉冲反馈信号，对于每个n，脉冲反馈信号包括脉冲，该脉冲的幅度与采样时刻nT处的数字输出信号的采样成比例，并且在时刻（n + ±2）T和（n +2）T，其中0 <±2 <1 <2。 第一DAC（10a）位于第一反馈回路中，第二DAC（10b）位于第二反馈回路中，第二反馈回路是相对于第一反馈回路的外部反馈回路。 还公开了相应的无线电接收机电路，相应的集成电路和相应的无线电通信装置。

公开(公告)号：EP3093993A2

公开(公告)日：2016-11-16

申请号：EP16159599.6

申请日：2016-03-10

Applicant: MediaTek, Inc

Inventor： HO, Chen-Yen ,  LIN, Yu-Hsin

IPC: H03K3/356 ,  H03M1/08

CPC classification number: H03K3/356113 ,  H03K3/356121 ,  H03K3/356191 ,  H03M1/066 ,  H03M1/0872 ,  H03M1/66 ,  H03M3/464

Abstract: A latch circuit (300) includes an input stage (310), an amplifying stage (MN1, MN2, MP1, MP2) and a clock gating circuit (320). The input stage (310) is arranged for receiving at least a clock signal and a data control signal. The amplifying stage (MN1, MN2, MP1, MP2) is coupled to the input stage (310) and supplied by a supply voltage and a ground voltage, and is arranged for retaining a data value and outputting the data value according to the clock signal and the data control signal. The clock gating circuit (320) is coupled to the amplifying stage (MN1, MN2, MP1, MP2), and is arranged for avoiding a short-circuit current between the supply voltage and the ground voltage.

Abstract translation: 锁存电路（300）包括在输入级（310），以放大级（MN1，MN2，MP1，MP2）和时钟选通电路（320）。 输入级（310）被布置为接收至少一个时钟信号和数据控制信号。 所述放大级（MN1，MN2，MP1，MP2）被耦合到所述输入级（310）和由电源电压和接地电压，并且被布置用于保持的数据值，并输出婷dataValue雅丁于时钟信号 和数据控制信号。 时钟选通电路（320）被耦合到所述放大级（MN1，MN2，MP1，MP2），并且被设置用于避免在电源电压和接地电压之间的短路电流。

公开(公告)号：EP2926459A4

公开(公告)日：2016-07-27

申请号：EP13859273

申请日：2013-11-20

Applicant: ANALOG DEVICES INC

Inventor： NGUYEN KHIEM QUANG ,  ADAMS ROBERT

IPC: H03M1/06 ,  H03M1/74

CPC classification number: H03M1/66 ,  H03M1/0668 ,  H03M1/067 ,  H03M1/74 ,  H03M3/464

Abstract: A multi-bit digital to analog converter comprising a plurality of unit cells, each providing an electrical signal to a common output at multiple levels in response to a respective control signal and a control system having multiple layers of branch circuits. Each branch circuit comprises a dynamic element matching circuit receiving a plurality of least significant bits of an input code to generate respective output signals to the control system and a plurality of branches, each receiving most significant bits of an input code to the respective layer and having an adder for the most significant bits of the layer's input signal and a respective output from the dynamic element matching circuit. An input signal to the digital to analog converter is input to a first layer as that layer's input code, input codes of the other layers are taken from output signals of preceding layers, and output signals of a last layer may be input to the unit cells as control signals.

公开(公告)号：EP3001569A1

公开(公告)日：2016-03-30

申请号：EP15181607.1

申请日：2015-08-19

Applicant: Analog Devices Global

Inventor： CALDWELL, Trevor Clifford ,  PETERSEN, Corey ,  SHIBATA, Hajime

IPC: H03M3/00

CPC classification number: H02H7/12 ,  H03M3/30 ,  H03M3/36 ,  H03M3/464 ,  H03M3/484

Abstract: Delta-sigma modulators do not handle overload well, and often become unstable if the input goes beyond the full-scale range of the modulator. To provide overload protection, an improved technique embeds an overload detector in the delta sigma modulator. When an overload condition is detected, coefficient(s) of the delta sigma modulator is adjusted to accommodate for the overloaded input. The improved technique advantageously allows the delta sigma modulator to handle overload gracefully without reset, and offers greater dynamic range at reduced resolution. Furthermore, the coefficient(s) of the delta sigma modulator can be adjusted in such a way to ensure the noise transfer function is not affected.

Abstract translation: Delta-Σ调制器不能很好地处理过载，如果输入超出调制器的满量程范围，通常会变得不稳定。 为了提供过载保护，改进的技术将过载检测器嵌入到Δ-Σ调制器中。 当检测到过载条件时，调节ΔΣ调制器的系数以适应过载输入。 改进的技术有利地允许Δ-Σ调制器在没有复位的情况下优雅地处理过载，并且以降低的分辨率提供更大的动态范围。 此外，可以以这样的方式调整Δ-Σ调制器的系数，以确保噪声传递函数不受影响。

公开(公告)号：EP2974029A1

公开(公告)日：2016-01-20

申请号：EP14712148.7

申请日：2014-03-06

Applicant: Microchip Technology Incorporated

Inventor： QUIQUEMPOIX, Vincent

IPC: H03M1/06 ,  H03M3/04

CPC classification number: H03M1/0665 ,  H03M3/424 ,  H03M3/464

Abstract: A digital-to analog converter (DAC) of the charge transfer type can be used in a sigma delta modulator for generating N output levels, wherein an output level is defined by a respective amount of charge transferred by the DAC. The DAC has a first capacitor switch unit receiving a reference voltage and a first digital input value to transfer first output charges, at least one second capacitor switch unit receiving the reference voltage and a second digital input value, wherein an output of the second capacitor switch unit is coupled in parallel with an output of the first capacitor switch unit to generate a sum of first and second transferred output charges; and a sequencer controlling switches of the first and second capacitor switch units wherein switching sequences according to individual first and second digital input values are provided for every DAC input value to generate the N output levels.

公开(公告)号：EP2959589A1

公开(公告)日：2015-12-30

申请号：EP13706236.0

申请日：2013-02-21

Applicant: Telefonaktiebolaget L M Ericsson (Publ)

Inventor： MATTISSON, Sven ,  PALM, Mattias ,  ANDREANI, Pietro ,  ANDERSON, Martin

IPC: H03M3/00

CPC classification number: H03M3/464 ,  H03M3/344 ,  H03M3/368 ,  H03M3/454

Abstract: A frequency selective circuit configured to convert an analog input signal to a digital output signal comprises an analog-to-digital converter (44) to generate the digital output signal of the circuit based on an analog input signal to the analog-to-digital converter (44); a digital-to-analog converter (46, 47) to generate an analog feedback signal based on the digital output signal from the analog-to-digital converter (44), and an analog filter arranged to generate the analog input signal to the analog-to-digital converter based on the analog feedback signal and an analog input signal to the circuit. The analog filter comprises at least two integrators (41, 42) in series, each having a feedback path comprising the analog-to-digital converter (44) in cascade with a digital-to-analog converter (46, 47), so that the overall noise transfer function of the circuit has at least two zeros in addition to zeros in the noise transfer function of the analog-to-digital converter.

公开(公告)号：EP2936688A1

公开(公告)日：2015-10-28

申请号：EP12809825.8

申请日：2012-12-21

Applicant: Teledyne Dalsa B.V.

Inventor： SCHINKEL, Daniel ,  GROOTHEDDE, Wouter

IPC: H03M3/02

CPC classification number: H03M3/464 ,  H03F3/181 ,  H03F3/45 ,  H03F2200/03 ,  H03F2200/331 ,  H03F2203/45116 ,  H03F2203/45138 ,  H03M3/43 ,  H03M3/438 ,  H03M3/446

Abstract: The present invention is related to a sigma-delta analog-to-digital converter (ADC). It further relates to a method for designing and manufacturing a sigma-delta ADC, and to a digital control loop comprising the same. According to the present invention, part of the filtering function required for noise-shaping is implemented in the feedback path. By suitably distributing the poles over the forward and feedback paths, stable operation can be achieved while offering low latency.

公开(公告)号：EP2930849A1

公开(公告)日：2015-10-14

申请号：EP15159281.3

申请日：2015-03-16

Applicant: Analog Devices Global

Inventor： Zhao, Jialin ,  Schreier, Richard E. ,  Silva, Jose Barreiro ,  Shibata, Hajime ,  Yang, Wenhua W. ,  Dong, Yunzhi

IPC: H03M1/10 ,  H03M3/04 ,  H03M1/74

CPC classification number: H03M3/378 ,  H03M1/1019 ,  H03M1/1038 ,  H03M1/74 ,  H03M3/37 ,  H03M3/384 ,  H03M3/388 ,  H03M3/464

Abstract: Digital-to-analog converters (DACs) are used widely in electronics. The DACs are usually not ideal and typically exhibits errors, e.g., static mismatch errors. This disclosure describes a digital calibration technique for DAC static mismatch in continuous-time delta-sigma modulators (CTDSMs). The methodology utilizes the DAC unit elements (UEs) themselves to measure each other's mismatch. There are no extra circuitries except for the logic design inside DAC drivers or comparators. The methodology is an attractive calibration technique for high performance CTDSMs, especially for high speed system in multi-gigahertz range with low over-sampling rate (OSR).

Abstract translation: 数模转换器（DAC）广泛应用于电子产品。 DAC通常不是理想的，并且通常表现出错误，例如静态失配错误。 本公开描述了用于连续时间Δ-Σ调制器（CTDSM）中的DAC静态失配的数字校准技术。 该方法利用DAC单元元件（UE）本身来测量彼此的不匹配。 没有额外的电路，除了DAC驱动器或比较器中的逻辑设计。 该方法是高性能CTDSM的有吸引力的校准技术，特别是对于具有低过采样率（OSR）的多千兆赫兹范围内的高速系统。

公开(公告)号：EP2811654A2

公开(公告)日：2014-12-10

申请号：EP14001697.3

申请日：2014-05-14

Applicant: Linear Technology Corporation

Inventor： Trampitsch, Gerd

IPC: H03M3/00

CPC classification number: H03M3/472 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1225 ,  H03M3/30 ,  H03M3/39 ,  H03M3/458 ,  H03M3/464

Abstract: A method and an ADC circuit use multiple SD modulations on an analog value and apply digital post-processing of the pulse density modulation (PDM) streams from the SD modulations obtaining a higher resolution in the digital output value for a given oversampling ratio. SD ADC does not face the constraint of conversion time doubling for each additional bit of resolution. In one implementation, an SD ADC includes conversions in SD phase and a resolution-boosting phase. During SD phase, MSBs of the digital output value are generated from the sampled analog value using a first SD conversion. At the end of SD phase, the sampled analog value is reduced to "residual quantization error," which remains in a capacitor of an integrator of SD ADC. In resolution-boosting phase, the LSBs of the digital output value are generated from residual quantization error using a second SD conversion that provides at least the LSBs.

Abstract translation: 方法和ADC电路对模拟值使用多个SD调制，并对来自SD调制的脉冲密度调制（PDM）流进行数字后处理，以获得给定过采样比的数字输出值中的更高分辨率。 SD ADC不会面临每增加一位分辨率的转换时间加倍的限制。 在一个实现中，SD ADC包括SD相位和分辨率提升阶段的转换。 在SD阶段，数字输出值的MSB使用第一个SD转换从采样的模拟值生成。 在SD阶段结束时，采样的模拟值被降低到“残余量化误差”，该残余量化误差保留在SD ADC的积分器的电容器中。 在分辨率提升阶段，数字输出值的LSB由残余量化误差产生，使用至少提供LSB的第二个SD转换。

公开(公告)号：EP1869771B1

公开(公告)日：2009-11-18

申请号：EP05735837.6

申请日：2005-04-15

Applicant: Semtech International AG

Inventor： NYS, Olivier

IPC: H03M1/12 ,  H03M3/00

CPC classification number: H03M3/384 ,  H03M3/464