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136 条记录 (耗时 0.012 秒)

    Process and apparatus for manufacturing MOS device
    61.
    发明公开
    Process and apparatus for manufacturing MOS device 失效
    的装置和方法的MOS器件的制造中。

    公开(公告)号：EP0602995A2

    公开(公告)日：1994-06-22

    申请号：EP93310226.1

    申请日：1993-12-17

    申请人： SHIN-ETSU HANDOTAI COMPANY LIMITED

    发明人： Fujimaki, Nobuyoshi, c/o Shin-Etsu Hand. Co., Ltd

    IPC分类号： H01L21/316 ,  H01L21/3105 ,  C30B33/00

    CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  Y10S438/909 ,  Y10S438/935

    摘要： In a process and apparatus for manufacturing a MOS device, a first clearance speed (X) of an annealing gas and optionally also of an oxidising gas, defined as the ratio of the flow rate to the area of clearance between a semiconductor wafer (4) and the interior surface of a tube (2) of a furnace (1) is controlled, e.g. to be at least 30 cm/min, while the semiconductor wafer is annealed and, optionally, oxidised. A second clearance speed (Y) of annealing gas is also controlled, e.g. to be at least 100 cm/min, while the semiconductor wafer is taken out of the tube. Further, the relation between X and Y is controlled, e.g. so that Y s -2.5 X + 275. The process and the apparatus reduce and control the fixed-charge density in the oxide film of a MOS device, with high repeatability.

    GaAs mesfets with enhanced schottky barrier
    63.
    发明公开
    GaAs mesfets with enhanced schottky barrier 失效
    GAAS MESFETS与增强肖特基屏障

    公开(公告)号：EP0517443A3

    公开(公告)日：1993-09-29

    申请号：EP92304899.5

    申请日：1992-05-29

    申请人： AT&T Corp.

    发明人： Emerson, Adrian Bruce ,  Ren, Fan

    IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/306

    CPC分类号： H01L21/02052 ,  H01L21/28581 ,  H01L29/66863 ,  Y10S438/906 ,  Y10S438/909

    摘要： The Schottky barrier gate (8) contact is produced by wet-chemical removal of native oxide in a sealed inert gas ambient and blow-drying the wet-etched surface with the inert gas prior to deposition of gate electrode metal on GaAs (4) by electron beam evaporation in an inert gas ambient. Use of Pt, the gate contact metal results in a Schottky barrier height of 0.98 eV for Pt on n-type GaAs (0.78 eV). To lower the sheet resistivity of the gate contact, Pt is preferably used as a multi-layer contact in combination with metals having lower sheet resistivity, e.g. Pt Au belayer.

    Method of manufacturing a semiconductor device comprising a capacitor with a ferroelectric dielectric, and semiconductor device comprising such a capacitor
    65.
    发明公开
    Method of manufacturing a semiconductor device comprising a capacitor with a ferroelectric dielectric, and semiconductor device comprising such a capacitor 失效
    一种用于与包括具有这样的电容器的铁电Dieletrikum和半导体器件的电容器的制造半导体器件的工艺。

    公开(公告)号：EP0513894A2

    公开(公告)日：1992-11-19

    申请号：EP92201215.8

    申请日：1992-05-04

    申请人： Philips Electronics N.V.

    发明人： Wolters, Robertus Adrianus Maria ,  Larsen, Poul Kjaerby ,  Ulenaers, Mathieu Joseph Emanuel

    IPC分类号： H01L29/92

    CPC分类号： H01L27/11502 ,  H01L28/55 ,  H01L29/49 ,  Y10S438/909

    摘要： A method of manufacturing a semiconductor device whereby a capacitor (2) is provided on a surface (10) of a semiconductor body (3) with a semiconductor element (1) in that a lower electrode (11), an oxidic ferroelectric dielectric (12) and an upper electrode (13) are provided in that order, the upper electrode not covering an edge of the dielectric, after which an insulating layer (14) with superimposed metal conductor tracks is provided. According to the invention, the edge of the dielectric (12) not covered by the upper electrode (13) is coated with a coating layer (14, 20, or 30) practically imperviable to hydrogen, after which the device is heated in a hydrogen-containing atmosphere. Heating in a hydrogen atmosphere neutralizes dangling bonds which arise during deposition of the conductor tracks on the insulating layer, while the coating layer protects the dielectric from attacks by hydrogen. The semiconductor device then has a shorter access time.

    摘要翻译： 一种制造半导体器件，其中的电容器（2）与（1）做了氧化物铁电电介质的下部电极（11）的半导体元件设置在半导体主体（3）的表面（10）上的12所述的方法（ ）和上部电极（13）以该顺序被设置，上部电极不是在电介质，afterwhich在绝缘带有叠加金属导体轨迹层（14）设置的端部覆盖。 。根据本发明，电介质（12）未包括的上部电极（13）的边缘涂覆有涂层（14，20，或30）氢实际上imperviable到，afterwhich设备在氢中加热 含氛围。 在氢气氛中加热氢中和在绝缘层上的导体轨迹的沉积过程中产生的悬挂键，而涂层层保护由攻击的电介质。 的半导体器件，然后具有更短的访问时间。

    Method for generation of ionized air
    67.
    发明公开
    Method for generation of ionized air 失效
    产生离子化空气的方法

    公开(公告)号：EP0476255A3

    公开(公告)日：1992-08-12

    申请号：EP91111599.6

    申请日：1991-07-12

    申请人： International Business Machines Corporation

    发明人： Batchelder, John S. ,  Gross, Vaughn P. ,  Gruver, Robert A. ,  Hobbs, Philip C.D. ,  Murray, Kenneth D.

    IPC分类号： H05F3/06 ,  H01L21/00 ,  H01L21/268

    CPC分类号： H01L21/67028 ,  H05F3/06 ,  Y10S430/138 ,  Y10S438/909

    摘要： Ionization of air is accomplished by use of a laser beam focussed to a small focal volume (20) of intense electric field adjacent an object to be discharged, e.g. a semiconductor chip or wafer (26). The electric field is sufficiently intense to ionize air. In the manufacture of a semiconductor circuit chip (26), during those steps which are conducted in an air environment, opportunity exists to remove from a surface (28) of a chip, or wafer, charge acquired during the manufacturing process. The ionized air is passed along the chip surface. Ions (24) in the air discharge local regions of the chip surface which have become charged by steps of a manufacturing process. By way of further embodiment of the invention, the ionization may be produced by injection of molecules of water into the air, which molecules are subsequently ionized by a laser beam and directed toward the chip via a light shield with the aid of a magnetic field.

    Diffusion of implanted dopant and polysilicon oxidation processes for VDMOS
    68.
    发明公开
    Diffusion of implanted dopant and polysilicon oxidation processes for VDMOS 失效
    Dotonstoff und Polysilizium-Oxydationsprozessefüreinen VDMOS的Diffendierung von implantiertem。

    公开(公告)号：EP0407704A1

    公开(公告)日：1991-01-16

    申请号：EP90109127.2

    申请日：1990-05-15

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Yawata, Shigeo, c/o Intellectual Property Division ,  Shibao, Kazuhisa, c/o Intellectual Property Div. ,  Hiraki, Shun-ichi, c/o Intellectual Property Div.

    IPC分类号： H01L21/225 ,  H01L21/321 ,  H01L21/336

    CPC分类号： H01L29/66712 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/321 ,  H01L21/32105 ,  H01L21/3221 ,  H01L29/42368 ,  H01L29/7802 ,  Y10S148/078 ,  Y10S438/907 ,  Y10S438/909

    摘要： In order to eliminate unwanted crystal defects gen­erated by an ion implantation, a semiconductor substrate (110) or an epitaxial layer (101), which is selectively subjected to an impurity ion implantation (107), is heat-treated in an inert gas atmosphere at 850 to 1050°C to recrystallize the implanted region (108). There­after, the semiconductor substrate (110) is heat-treated at 900 to 1250°C in an atmosphere containing oxygen. For eliminating abnormal growth of grain boundaries in a polycrystalline semiconductor layer (105, 105′) depo­sited on an insulating film (103, 104), the semiconduc­tor layer (105, 105′) is heat-treated at 900 to 1100°C in an atmosphere containing oxygen. By applying at least one of these processes to usual fabrication methods, semiconductor devices with high reliability such as power MOSFETs will be provided.

    摘要翻译： 为了消除由离子注入产生的不需要的晶体缺陷，选择性地进行杂质离子注入（107）的半导体衬底（110）或外延层（101）在惰性气体气氛中进行热处理 850至1050℃以重结晶注入区域（108）。 然后，在含有氧的气氛中，在900〜1250℃下对半导体基板（110）进行热处理。 为了消除沉积在绝缘膜（103,104）上的多晶半导体层（105,105分钟）中的晶界的异常生长，将半导体层（105,105分钟）在900〜1100℃下进行热处理 含氧气氛。 通过将这些处理中的至少一个应用于通常的制造方法，将提供诸如功率MOSFET的具有高可靠性的半导体器件。