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192 条记录 (耗时 0.013 秒)

    METHOD AND DEVICE
    1.
    发明授权
    METHOD AND DEVICE 有权
    方法和装置

    公开(公告)号：EP1665348B1

    公开(公告)日：2011-12-07

    申请号：EP03818592.2

    申请日：2003-09-05

    申请人： Cree Sweden AB

    发明人： HARRIS, Christopher ,  KONSTANTINOV, Andrei

    IPC分类号： H01L21/04 ,  H01L21/335 ,  H01L29/772

    CPC分类号： H01L29/66924 ,  H01L29/66068 ,  H01L29/66462 ,  H01L29/66863

    摘要： Method for producing a field effect transistor comprising a source region (9), a drain region and a channel layer (11) interconnecting the source and drain region. The method includes the step of providing a sacrificial layer (4) on part of a semiconductor material (1) whose edge is used to define the edge of an implant, such as the source region (9), in the semiconductor material (1), where the edge (4c) of the sacrificial layer (4) is subsequently used to define the edge of a gate (16).

    SELF-ALIGNED SILICON CARBIDE SEMICONDUCTOR DEVICES AND METHODS OF MAKING THE SAME
    3.
    发明公开
    SELF-ALIGNED SILICON CARBIDE SEMICONDUCTOR DEVICES AND METHODS OF MAKING THE SAME 有权
    SELF-ALIGNED碳化硅或氮化镓半导体元件AND METHOD FOR THEIR

    公开(公告)号：EP1726043A2

    公开(公告)日：2006-11-29

    申请号：EP05725593.7

    申请日：2005-03-14

    申请人： Semisouth Laboratories, Inc.

    发明人： SANKIN, Igor ,  CASADY, Janna B. ,  MERRETT, Joseph N.

    IPC分类号： H01L29/15

    CPC分类号： H01L29/66068 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/45 ,  H01L29/66863 ,  H01L29/8128

    摘要： A self-aligned silicon carbide power MESFET with improved current stability and a method of making the device are described. The device, which includes raised source and drain regions separated by a gate recess, has improved current stability as a result of reduced surface trapping effects even at low gate biases. The device can be made using a self-aligned process in which a substrate comprising an n+-doped SiC layer on an n-doped SiC channel layer is etched to define raised source and drain regions (e.g., raised fingers) using a metal etch mask. The metal etch mask is then annealed to form source and drain ohmic contacts. A single- or multilayer dielectric film is then grown or deposited and anisotropically etched. A Schottky contact layer and a final metal layer are subsequently deposited using evaporation or another anisotropic deposition technique followed by an optional isotropic etch of dielectric layer or layers.

    Method for forming a T-shaped gate electrode in a semi-conductor device, and the T-shaped gate electrode
    7.
    发明公开
    Method for forming a T-shaped gate electrode in a semi-conductor device, and the T-shaped gate electrode 失效
    在半导体器件中的T形栅电极的制造方法，以及所述T形栅电极

    公开(公告)号：EP0801418A2

    公开(公告)日：1997-10-15

    申请号：EP97105617.1

    申请日：1997-04-04

    申请人： MURATA MANUFACTURING CO., LTD.

    发明人： Sasaki, Hidehiko ,  Yokoi, Yasushi ,  Monden, Koji

    IPC分类号： H01L21/027 ,  H01L21/28 ,  H01L21/335 ,  H01L29/423

    CPC分类号： H01L29/66863 ,  H01L21/0272 ,  H01L21/28581 ,  H01L21/28587 ,  Y10S438/949 ,  Y10S438/951

    摘要： This invention provides a manufacturing method of T-shaped gate electrode (12') in a semiconductor device, comprising the steps of: forming a first resist (3) on a semiconductor substrate (1) on which source and drain electrodes (2) are provided; forming a first gate opening (6) on said first resist (3) between said source and drain electrodes (2); deforming said first resist (3) by baking; forming a second resist (7) overlaying said first resist (3) and said first gate opening (6); forming a second gate opening (10) on said second resist (7) above said first gate opening (6), said second gate opening (10) being larger than said first gate opening (6); depositing electrode metal (11) for forming the T-shaped gate electrode (12') on said second gate opening (10); and removing said first and second resist (3,7), which is characterized in that a pair of dummy openings (6') are formed on said first resist (3) in proximity to both sides of said first gate opening (6), and a pair of first resist convex portions are formed when said first resist (3) are deformed by baking. This invention also provides a T-shaped gate electrode (12') in a semiconductor device, characterized in that the T-shaped gate electrode (12') is analogous to V-shape and a rise angle thereof is 30 degrees or more with respect to the surface of said semiconductor substrate (1). The T-shaped gate electrode of this invention and manufactured by this invention can reduce parasitic capacitance between the gate electrode 12 and the semiconductor substrate 1.

    Methods of fabrication of submicron features in semiconductor devices
    8.
    发明公开
    Methods of fabrication of submicron features in semiconductor devices 失效
    在Halbleiterbauelementen的Verfahren zur Herstellung von submikrometrischen Merkmalen

    公开(公告)号：EP0782183A2

    公开(公告)日：1997-07-02

    申请号：EP96119205.1

    申请日：1996-11-29

    申请人： MOTOROLA, INC.

    发明人： Hashemi, Majid M. ,  Tehrani, Saied N. ,  Pack, Sung P.

    IPC分类号： H01L21/338 ,  H01L21/335 ,  H01L21/285

    CPC分类号： H01L29/66863 ,  H01L21/28132 ,  H01L21/28581 ,  H01L29/42316 ,  H01L29/66462 ,  Y10S438/947

    摘要： A process of fabricating submicron features including depositing a gate metal layer (15) on a substrate (10) and forming a first etchable layer (20) of material on the metal layer (15) to define a first sidewall (21). A second etchable layer (25) is deposited on the structure so as to define a second sidewall (26). The second etchable layer (25) is etched so as to leave only the second sidewall (26) and the first etchable layer (20) is removed. The metal layer (15) is etched using the second sidewall (26) as an etch mask to form a submicron feature. The width of the feature depends upon the thickness of the metal layer (15).

    摘要翻译： 制造具有亚微米特征的半导体结构包括：提供具有平坦表面和表面不连续性的半导体结构; 在表面上沉积导电材料层和不连续; 在所述导电层上形成第一可蚀刻材料层，以限定邻近所述结构不连续处的第一侧壁; 在所述导电层上和所述第一可蚀刻层上形成第二可蚀刻材料层，所述第二可蚀刻层覆盖所述第一可蚀刻层中的侧壁并在所述第二可蚀刻层中形成比所述第二可蚀刻层的剩余部分厚的第二侧壁 可蚀刻层; 从导电层和第一可蚀刻层蚀刻第二可蚀刻层，以便将第二侧壁的一部分留在第二可蚀刻层中; 去除所述第一可蚀刻层以使所述第二可蚀刻层中的所述第二侧壁与所述半导体结构的不连续部分间隔开; 使用第二侧壁蚀刻表面上的材料的导电层和结构的不连续性，以形成亚微米特征; 移除第二侧壁。

    Field effect transistor having comb-shaped electrode assemblies
    10.
    发明公开
    Field effect transistor having comb-shaped electrode assemblies 失效
    具有梳状电极组件的场效应晶体管

    公开(公告)号：EP0724296A2

    公开(公告)日：1996-07-31

    申请号：EP96101140.0

    申请日：1996-01-26

    申请人： NEC CORPORATION

    发明人： Kanamori, Mikio ,  Imamura, Takafumi

    IPC分类号： H01L29/423 ,  H01L29/417 ,  H01L21/338 ,  H01L23/482

    CPC分类号： H01L29/66863 ,  H01L21/28587 ,  H01L23/4824 ,  H01L24/05 ,  H01L29/41758 ,  H01L29/42316 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/48465 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/00

    摘要： A FET has comb-shaped electrode assemblies for source, drain and gate of the FET. Each of the source and drain electrode assemblies has a plurality of electrodes contacting the active region of the FET and formed as a first layer metal laminate, and a bus bar connecting the electrodes together to a corresponding pad and formed as a second layer metal laminate. The gate electrode layer has a plurality of gate electrodes contacting the active layer in Schottky contact, a gate bus bar connecting the gate electrodes together, a gate pad connected to the gate bus bar. The gate bus bar is formed as a first layer metal laminate intersecting the stem portion of the comb-shaped source bus bar. The two-layer metal structure of the FET reduces the number of photolithographic steps and thereby fabrication costs of the FET.

    摘要翻译： FET具有用于FET的源极，漏极和栅极的梳状电极组件。 源电极和漏电极组件中的每一个具有接触FET的有源区并形成为第一层金属层压板的多个电极，以及将电极连接到相应的焊盘并形成为第二层金属层压板的汇流条。 栅电极层具有以肖特基接触接触有源层的多个栅电极，将栅电极连接在一起的栅极母线，连接至栅极母线的栅极焊盘。 栅极汇流条形成为与梳形源极汇流条的杆部分交叉的第一层金属层压板。 FET的两层金属结构减少了光刻步骤的数量，从而减少了FET的制造成本。