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754 条记录 (耗时 0.016 秒)

    Array architecture for long record length FISO memory
    62.
    发明公开
    Array architecture for long record length FISO memory 审中-公开
    用于数据记录大长度的磁道的FISO存储器的矩阵布置

    公开(公告)号：EP1047080A1

    公开(公告)日：2000-10-25

    申请号：EP00301107.9

    申请日：2000-02-14

    申请人： Tektronix, Inc.

    发明人： Kogan, Grigory

    IPC分类号： G11C27/02 ,  G11C27/04

    CPC分类号： G11C27/04 ,  G11C27/024

    摘要： A very long linear input array capable of acquiring long series of acquisition data is achieved by breaking the long linear array into a series of sub-arrays, each enabled by a "global" set of enable signals. The individual cells of the local arrays are addressed by local x-y enable signals. This arrangement permits the acquisition of very long record lengths, without sacrificing the quality of other aspects of the acquisition process to excess capacitance.

    Code division multiplex communication system
    63.
    发明公开
    Code division multiplex communication system 失效
    Kodemultiplexnachrichtenübertragungssystem

    公开(公告)号：EP0859471A3

    公开(公告)日：2000-03-01

    申请号：EP98300644.6

    申请日：1998-01-29

    申请人： CLARION Co., Ltd.

    发明人： Tsubouchi, Kazuo ,  Masu, Kazuya ,  Fujita, Yasuhito, c/o Alps Electric Co Ltd

    IPC分类号： H04B1/707 ,  H04J13/04 ,  G11C19/28 ,  G11C27/02

    CPC分类号： H04B1/7093

    摘要： A code division multiplex communications system comprises: receiving means (1,2) for receiving a radio wave and transforming the radio wave to an electric signal; voltage-current converting means (101) for converting the electric signal to a current signal; current delaying means (102, 102 2 ... 102 n ) for sequentially reading the electric signal at a timing of a clock pulse; adding and subtracting means (105) for adding and subtracting output currents of the current delaying means in accordance with a spread code; and reproducing means (107) for reproducing a transmission signal on the basis of an output of the adding and subtracting means.

    AUSTASTSCHALTUNG
    64.
    发明公开
    AUSTASTSCHALTUNG 有权

    公开(公告)号：EP0979511A1

    公开(公告)日：2000-02-16

    申请号：EP99903621.3

    申请日：1999-01-12

    申请人： LITEF GmbH

    发明人： RAU, Ernst

    IPC分类号： G11C27/02

    CPC分类号： G11C27/026

    摘要： The aim of the invention is to provide a means of carrying out essentially glitch-free blanking for analog signal values which occur in a periodical sequence and which are to be capacitively temporarily stored. Said signal values are digitised by an A/D converter (5) and are then to be erased in a capacitive temporary memory (2) before the next signal value occurs. According to the invention, a first OTA (operational transconductance amplifier) (11) which can be activated by a blanking pulse is provided. The non-inverting input (+) of said OTA is connected to the base point of the capacitive memory (2) and its output is connected to the charging connection (A) of the capacitive memory whilst the inverting input (-) is connected to the charging connection (A) of the capacitive memory (A) via an impedance converter (13) and a resistor (12) which limits the discharge current. A second OTA (10) serves as a signal driver whose degree of amplification is predetermined by the relationship between a resistor (1) which lies parallel to the capacitive memory (2) and a series resistor which determines the potential at the inverting input (-) of the second OTA (10).

    EP0925588A4 -
    65.
    发明公开
    EP0925588A4 - 失效
    EP0925588A4 - Google专利

    公开(公告)号：EP0925588A4

    公开(公告)日：1999-07-21

    申请号：EP97940818

    申请日：1997-09-04

    IPC分类号： G11C27/02 ,  H03K17/16

    CPC分类号： G11C27/028

    摘要： The current cell includes a first (M2) and second (M1) MOS transistor connected in series between a constant current source (51) and a reference ground. Each of the two MOS transistor has a respective first (59) and second (63) switch coupling its control gate to its drain. The sample phase of a sample and hold operation is broken down into a first and second sample sub-phase, and an input current (Iin) maintained applied to the current cell during both sample sub-phases. During the first sample sub-phase, the second MOS transistor (M1) memorizes a gate voltage corresponding to the input current (Iin), constant current source (51) and a clock feedthrough error. A modulation voltage (Vmod) is induced at the drain (62) of the second transistor (M1) as a result of the channel effect, and the first MOS transistor (M2) is used to store and maintain this modulation voltage (Vmod) at the drain (62) of the second MOS transistor (M1) during the hold phase.

    摘要翻译： 电流单元包括串联连接在恒流源（51）和参考地之间的第一（M2）和第二（M1）MOS晶体管。 两个MOS晶体管中的每一个具有将其控制栅极耦合到其漏极的相应第一（59）和第二（63）开关。 采样和保持操作的采样阶段被分解为第一和第二采样子阶段，并且在两个采样子阶段期间保持施加到当前单元的输入电流（Iin）。 在第一采样子阶段期间，第二MOS晶体管（M1）存储对应于输入电流（Iin），恒流源（51）和时钟馈通误差的栅极电压。 作为沟道效应的结果，在第二晶体管（M1）的漏极（62）处感应出调制电压（Vmod），并且第一MOS晶体管（M2）用于将该调制电压（Vmod）存储并保持在 在保持阶段期间第二MOS晶体管（M1）的漏极（62）。

    A sample-and-hold circuit
    66.
    发明公开
    A sample-and-hold circuit 失效
    采样保持电路

    公开(公告)号：EP0875904A3

    公开(公告)日：1999-07-21

    申请号：EP98303366.3

    申请日：1998-04-30

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Nagaraj, Krishnaswamy

    IPC分类号： G11C27/02

    CPC分类号： G11C27/024 ,  G11C27/026 ,  H03K17/063 ,  H03K17/165

    摘要： A MOS track-and-hold circuit incorporating cancellation of error due to switch feedthrough is described. To eliminate the channel charge feedthrough due to oxide capacitance, a switched capacitor source (22) is connected to be charged to a voltage V1 during the "hold" phase and between the input node (12) and the switch gate (17) to provide a voltage V1 - Vin during the "track" phase. A dummy transistor (26) biased in an "off" condition has its drain connected to the holding capacitor (15) and its gate switched between ground and the output terminal (Vout which tracks Vin) to also cancel the feedthrough from the gate-drain overlap capacitance and any gate-drain parasitic capacitance.

    Low voltage sample and hold circuits
    68.
    发明公开
    Low voltage sample and hold circuits 有权
    低电压采样和保持电路

    公开(公告)号：EP0920031A2

    公开(公告)日：1999-06-02

    申请号：EP98308344.5

    申请日：1998-10-13

    申请人： LUCENT TECHNOLOGIES INC.

    发明人： Vallancourt, David Gerard

    IPC分类号： G11C27/02

    CPC分类号： G11C27/02

    摘要： A sampling circuit which is capable of a full ranging output when powered with very low voltage supplies, e.g., of about 1 volt, includes a current copier function added to a sample and hold circuit to avoid the need for low threshold switching devices in the sampling circuit, thus avoiding output droop due to the increased leakage of low threshold devices. A pre-charge circuit (100) is placed between the sample and hold circuit (0A3, M1,C H ) and a current storage transistor (M3) to 'boost' the voltage level of the output of the sample and hold circuit above the threshold voltage of the current storage transistor. The pre-charge circuit includes an output voltage boost capacitor (C S ) which is charged before the hold cycle of the sampling circuit. The level of the voltage charged onto the output voltage boost capacitor is based on the threshold voltage of the current storage transistor.

    摘要翻译： 当采用例如大约1伏特的非常低电压电源供电时能够进行全范围输出的采样电路包括将电流复制器功能添加到采样和保持电路以避免采样中对低阈值开关器件的需要 电路，从而避免由于低阈值器件的泄漏增加而导致的输出下垂。 在采样和保持电路（0A3，M1，CH）和电流存储晶体管（M3）之间放置预充电电路（100），以将采样和保持电路的输出的电压电平“升高”到阈值之上 电流储存晶体管的电压。 预充电电路包括在采样电路的保持周期之前充电的输出电压提升电容器（CS）。 充入输出升压电容器的电压的电平基于电流存储晶体管的阈值电压。

    Analog delay circuit
    69.
    发明公开
    Analog delay circuit 失效
    AnalogeVerzögerungsschaltung

    公开(公告)号：EP0801399A3

    公开(公告)日：1999-04-21

    申请号：EP97302335.1

    申请日：1997-04-04

    申请人： SONY CORPORATION

    发明人： Katakura, Masayuki ,  Takeda, Masashi

    IPC分类号： G11C27/02

    CPC分类号： G11C27/026 ,  G11C7/02 ,  G11C27/024

    摘要： In an analog delay circuit having an analog-value memory circuit comprising memory cells arranged to form a matrix with each memory cell comprising a memory-cell capacitor and a select-switch device, read switches, write switches and reset switches are provided for the rows to form a read/write circuit. When a memory cell is selected, the capacitance of a parasitic capacitor connected to write and read nodes is reduced to the capacitance of a parasitic capacitor of one row selected by the select-switch device and, at the same time, electric charge accumulated in the parasitic capacitor of the selected row is reset by one of the reset switches provided for the selected row immediately prior to a read operation to read electric charge of the selected memory cell on the row, eliminating noise caused by the electric charge accumulated in the parasitic capacitor of the selected row.

    摘要翻译： 在具有模拟值存储电路的模拟延迟电路中，模拟值存储电路包括被布置为形成矩阵的存储器单元，每个存储单元包括存储单元电容器和选择开关器件，为行提供读取开关，写入开关和复位开关 以形成读/写电路。 当选择存储单元时，连接到写入和读取节点的寄生电容器的电容被减小为由选择开关器件选择的一行的寄生电容器的电容，并且同时累积在 所选行的寄生电容器在读取操作之前由为选定行提供的一个复位开关复位，以读取该行上所选择的存储单元的电荷，消除由寄生电容器中累积的电荷引起的噪声 的选定行。