公开(公告)号：EP2299485A1

公开(公告)日：2011-03-23

申请号：EP10009571.0

申请日：2010-09-14

申请人： Unisantis Electronics (Japan) Ltd.

发明人： Masuoka, Fujio ,  Arai, Shintaro

IPC分类号： H01L21/8244 ,  H01L27/02 ,  H01L27/11 ,  H01L21/336 ,  H01L29/768 ,  H01L29/78 ,  H01L21/02

CPC分类号： H01L29/7827 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1112 ,  H01L28/20

摘要： In a static memory cell configured using four MOS transistors and two load resistance elements, the MOS transistors are formed on diffusion layers formed on a substrate. The diffusion layers (103a, 103b) serve as memory nodes. The drain, gate and source of the MOS transistors ( Qa11, Qa21, Qd11, Qd21 ) are arranged in the direction orthogonal to the substrate, and the gate surrounds a columnar semiconductor layer. In addition, the load resistance elements ( Ra1, Rb1 ) are formed by contact plugs. In this way, it is possible to form a SRAM cell with a small area.

摘要翻译： 在使用四个MOS晶体管和两个负载电阻元件配置的静态存储单元中，在形成在衬底上的扩散层上形成MOS晶体管。 扩散层（103a，103b）用作存储器节点。 MOS晶体管（Qa11，Qa21，Qd11，Qd21）的漏极，栅极和源极被配置在与衬底正交的方向上，栅极包围柱状半导体层。 此外，负载电阻元件（Ra1，Rb1）由接触插塞形成。 以这种方式，可以形成具有小面积的SRAM单元。

公开(公告)号：EP1103074B1

公开(公告)日：2010-01-06

申请号：EP99937597.5

申请日：1999-07-28

申请人： Rovec Acquisitions Ltd. L.L.C.

发明人： HEBERT, François

IPC分类号： H01L29/76 ,  H01L29/788 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/148 ,  H01L29/00 ,  H01L29/768 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/20 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L21/2815 ,  H01L29/402 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7835

摘要： A MOSFET has a buried shield plate under the gate and over the drain with the gate being formed on the periphery of the buried shield plate as a self-aligned structure with minimal or no overlap of the gate over the shield plate. Methods of fabricating the MOSFET are disclosed.

公开(公告)号：EP2044628A2

公开(公告)日：2009-04-08

申请号：EP07810270.4

申请日：2007-07-09

申请人： Eastman Kodak Company

发明人： PARKS, Christopher

IPC分类号： H01L27/146 ,  H01L27/148 ,  H01L29/768 ,  H04N3/15 ,  H04N9/04

CPC分类号： H01L29/768 ,  H01L27/14621 ,  H01L27/14831 ,  H01L27/14887 ,  H04N5/335 ,  H04N5/3458 ,  H04N5/347 ,  H04N5/37213 ,  H04N9/045

摘要： An image sensor includes a plurality of pixels overlaid with a color filter pattern of at least two colors having the same color on every other pixel in one direction; three or more charge-coupled devices oriented parallel to the every other pixel color filter repeat pattern; a charge sensing amplifier at the output of at least two of the charge couple devices; each charge-coupled device having a first and a second gate; a CCD-to-CCD transfer gate connecting adjacent charge-coupled devices with the first gate being on one side of the CCD-to-CCD transfer gate and the second gate being on the opposite side of the CCD-to-CCD transfer gate; all CCD-to-CCD transfer gates are electrically connected together; all first gates are electrically connected; and all second gates are electrically connected.

公开(公告)号：EP1897146A2

公开(公告)日：2008-03-12

申请号：EP06785622.9

申请日：2006-06-27

申请人： Lamina Lighting, Inc.

发明人： MAZZOCHETTE, Joseph

IPC分类号： H01L29/768

CPC分类号： H05K1/021 ,  H01L25/0753 ,  H01L33/486 ,  H01L33/641 ,  H01L2224/48137 ,  H01L2224/48227 ,  H05K1/141 ,  H05K1/182 ,  H05K3/0061 ,  H05K3/3442 ,  H05K3/403 ,  H05K2201/09127 ,  H05K2201/09181 ,  H05K2201/09845 ,  H05K2201/10106 ,  H05K2203/063 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T156/13

摘要： A light emitting diode (LED) package for high temperature operation which includes a printed wire board and a heat sink. The LED package may include a formed heat sink layer, which may be thermally coupled to an external heat sink. The printed wire board may include apertures that correspond to the heat sink such that the heat sink is integrated with the printed wire board layer. The LED package may include castellations for mounting the package on a secondary component such as a printed wire board. The LED package may further comprise an isolator disposed between a base metal layer and one or more LED die. Optionally, the LED die may be mounted directly on a base metal layer. The LED package may include a PWB assembly having a stepped cavity, in which one or more LED die are disposed. The LED package is advantageously laminated together using a pre-punched pre-preg material or a pressure sensitive adhesive.

公开(公告)号：EP1755166A2

公开(公告)日：2007-02-21

申请号：EP06023938.1

申请日：2002-03-14

申请人： SONY CORPORATION

发明人： Iizuka, Takayuki ,  Yamashita, Mitsuru

IPC分类号： H01L27/148 ,  H01L29/768 ,  H01L27/146

CPC分类号： H01L27/14812 ,  H01L27/14603 ,  H01L27/14609 ,  H01L29/76816

摘要： Signal charges generated by a plurality of photoelectric conversion elements are transferred to first and second horizontal charge transfer registers via corresponding vertical charge transfer registers. The first and second horizontal charge transfer registers transfer the signal charges to first and second output portions, respectively. The first and second output portions convert the signal charges into voltages. The first and second output portions respectively include first and second signal charge detectors, first and second transistors each having a source, a drain, and a gate, and first and second charge sweeping regions, each having a charge sweeping control gate and a charge sweeping drain. The first signal charge detector, the source, the drain, and the gate of the first transistor, and the charge sweeping control gate and the charge sweeping drain of the first charge sweeping region are almost congruent to the second signal charge detector, the source, the drain, and the gate of the second transistor, and the charge sweeping control gate and the charge sweeping drain of the second charge sweeping region, and the former components are overlaid almost completely on the latter components by a translational movement.

摘要翻译： 由多个光电转换元件生成的信号电荷通过相应的垂直电荷转移寄存器传送到第一和第二水平电荷转移寄存器。 第一和第二水平电荷转移寄存器将信号电荷分别转移到第一和第二输出部分。 第一和第二输出部分将信号电荷转换为电压。 第一和第二输出部分分别包括第一和第二信号电荷检测器，每个具有源极，漏极和栅极的第一和第二晶体管以及第一和第二电荷扫描区域，每个具有电荷扫描控制栅极和电荷扫描 排水。 第一信号电荷检测器，第一晶体管的源极，漏极和栅极以及第一电荷扫描区域的电荷扫描控制栅极和电荷扫描漏极几乎与第二信号电荷检测器，源极， 第二晶体管的漏极和栅极以及第二电荷扫描区域的电荷扫掠控制栅极和电荷扫掠漏极，并且前面的部件通过平移运动几乎完全覆盖在后面的部件上。

公开(公告)号：EP1743339A2

公开(公告)日：2007-01-17

申请号：EP05740193.7

申请日：2005-04-28

申请人： MICRON TECHNOLOGY, INC.

发明人： BHATTACHARYYA, Arup

IPC分类号： G11C11/00 ,  H01L29/768

CPC分类号： H01L27/1027 ,  G11C11/39 ,  G11C16/349 ,  H01L21/28273 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/7436 ,  H01L29/749 ,  H01L29/87

摘要： Disclosed herein is an improved thyristor-based memory cell. In one embodiment, the cell (10) is formed in a floating substrate using Silicon-On-Insulator (SOI) technology. The cell preferably incorporates a lateral thyristor (20) formed entirely in the floating substrate, and which is gated by a second word line. The cathode of the thyristor also comprises a source of an access transistor (18), whose drain is connected to the bit line of the device, and which is gated by a first word line (14). A trapping layer is built into the floating substrate, and when writing to the cell, pulses are added to cause holes to be trapped on the trapping layer for a logic state ‘1’ and to cause electrons to be trapped on the trapping layer for a logic state ‘0’. Trapping of charges on the trapping layer adds extra margin to the stored data states, prevents their degradation, and renders the cell non-volatile.

公开(公告)号：EP1721337A1

公开(公告)日：2006-11-15

申请号：EP05716754.6

申请日：2005-02-21

申请人： Atmel Grenoble S.A.

发明人： BLANCHARD, Pierre, THALES

IPC分类号： H01L29/768

CPC分类号： H01L29/76816

摘要： The invention relates to conductive integrated circuits disposed above a semiconductor substrate and a diode formed between two electrodes. In order to obtain a very small-sized diode, the following steps are carried out: creation of the electrodes (ELn, GRST), thermal oxidation of the electrodes then the substrate between the electrodes is bared, followed by the operations enumerated below: a) deposition of doped polycrystalline silicon in order to form a pole (42) of the diode, wherein the substrate forms the other pole; b) definition of a desired silicon pattern (14) covering the space left between the electrodes and also covering a region located outside said space; c) deposition of an insulating layer (18), local etching of an opining in said insulating layer above the polycrystalline silicon outside the space located between the electrodes, in order to form a displaced contact area, deposition of a metal coating and etching of the metal coating. The main application of the invention is the reading diode for a CCD-type reading register.

公开(公告)号：EP0860027B1

公开(公告)日：2005-02-16

申请号：EP97929458.4

申请日：1997-07-17

申请人： DALSA CORPORATION

发明人： PEEK, Hermanus, Leonardus ,  VERBUGT, Daniel, Wilhelmus, Elisabeth

IPC分类号： H01L29/768 ,  H01L29/207 ,  H01L21/22 ,  H01L21/339

CPC分类号： H01L29/66954 ,  H01L29/42396

摘要： It is known in charge coupled devices to use a dual layer of silicon oxide and silicon nitride as the gate dielectric. Since silicon nitride is practically impermeable to hydrogen, the nitride layer is usually provided with openings through which hydrogen can penetrate up to the surface of the silicon body during the annealing step carried out for passivating the surface. The openings in the nitride layer are provided by a known method, with gates in a first poly layer serving as a mask, in that the nitride is removed from between these gates and an oxidation step is subsequently carried out. According to the invention, the openings in the nitride layer are formed by means of a separate mask (20), such that the edges of the openings (9) in the nitride layer (8) lie at some distance from the edges of the gates. It was found that the dark current can be substantially reduced by this method, and that in addition quantities such as the fixed pattern noise and the number of white spots can be advantageously reduced.

公开(公告)号：EP0886321B1

公开(公告)日：2004-09-15

申请号：EP98114675.6

申请日：1995-07-13

申请人： SONY CORPORATION

发明人： Hirota, Asao

IPC分类号： H01L29/792 ,  H01L29/768 ,  H01L21/28 ,  G11C19/28

CPC分类号： H03F1/301 ,  G11C5/146 ,  H01L29/76833 ,  H01L29/792 ,  H03F3/345 ,  H03K19/0027 ,  H03K2217/0018

公开(公告)号：EP1353383A2

公开(公告)日：2003-10-15

申请号：EP03252142.9

申请日：2003-04-04

申请人： VICTOR COMPANY OF JAPAN, LTD.

发明人： Miyahara, Hiroyuki

IPC分类号： H01L27/148 ,  H01L29/768

CPC分类号： H04N5/3415 ,  H01L27/14831 ,  H01L29/76816 ,  H04N5/3595 ,  H04N5/361 ,  H04N5/3653 ,  H04N5/372 ,  H04N5/37213

摘要： An image-sensing device has pixel areas for outputting CCD signals of plural channels, and an adjusting portion for adjusting a level of each channel of the CCD signals outputted from the pixel area. A first channel CCD signal is provided from a pixel area 11a, a horizontal OB area 15a, a slide shift area 12a, and an HCCD 13a. A second channel CCD signal is provided from a pixel area 11b, a horizontal OB area 15b, a slide shift area 12b, and an HCCD 13b. Both of the first and second CCD signals are supplied to the adjusting portion with a reference signal added. The adjusting portion controls CCD signal of each channel by making the level of reference signal the same. The variation of the shift efficiency of electric charge in the border of pixel areas 11a and 11b for each channel, and in the slide shift areas 13a and 13b can be compensated.

摘要翻译： 图像感测装置具有用于输出多个通道的CCD信号的像素区域和用于调整从像素区域输出的CCD信号的每个通道的电平的调整部分。 从像素区域11a，水平OB区域15a，滑动移动区域12a和HCCD 13a提供第一通道CCD信号。 从像素区域11b，水平OB区域15b，滑动移动区域12b和HCCD 13b提供第二通道CCD信号。 第一和第二CCD信号都被添加到参考信号到调节部分。 调整部通过使参考信号的电平相同来控制各通道的CCD信号。 可以补偿每个通道和滑动移动区域13a和13b中的像素区域11a和11b的边界中的电荷的偏移效率的变化。