公开(公告)号：EP3117491B1

公开(公告)日：2018-05-02

申请号：EP15718999.4

申请日：2015-03-13

Applicant: Texa S.p.A.

Inventor： FANTIN, Mauro ,  MARTINELLI, Igor

IPC: A41D1/08 ,  A41D13/01 ,  A41D15/00 ,  H01R13/66 ,  H01R12/57 ,  H01R12/58 ,  H05K1/11

CPC classification number: H01R13/6658 ,  A41D1/08 ,  A41D13/01 ,  A41D15/002 ,  A41D2600/102 ,  H01R12/57 ,  H01R12/58 ,  H01R2201/26 ,  H05K1/117 ,  H05K2201/09181 ,  H05K2201/1034

公开(公告)号：EP2712281A4

公开(公告)日：2015-06-24

申请号：EP12785591

申请日：2012-02-01

Applicant: NGK SPARK PLUG CO

Inventor： HASEGAWA MASAMI ,  HIRAYAMA SATOSHI ,  KITO NAOKI

IPC: H05K1/02 ,  H05K3/00

CPC classification number: H05K1/0306 ,  H05K1/113 ,  H05K3/0044 ,  H05K3/0052 ,  H05K3/381 ,  H05K3/403 ,  H05K2201/0909 ,  H05K2201/09181 ,  H05K2201/09845 ,  H05K2203/107 ,  Y10T29/49124 ,  Y10T428/24479 ,  Y10T428/24612

Abstract: Provided are a wiring substrate having few burrs in the vicinity of a notch located on a side surface of a substrate main body, in which breakage of a conductor layer provided on the inner wall of the notch is suppressed; a multi-piece wiring substrate array for providing a plurality of the wiring substrates; and a method for reliably producing the multi-piece wiring substrate array. The wiring substrate 1a includes a substrate main body kp which is formed of a plurality of stacked ceramic layers S, which has a rectangular shape in plan view, which has a pair of opposite first and second main surfaces 3 and 2, and which has side surfaces 4 each being located between the paired main surfaces 3 and 2, and having a groove surface 6 located on a side toward the first main surface (back surface) 3 and a fracture surface 5 located between the groove surface 6 and the second main surface 2; and a notch 11 which has a concave shape in plan view, and which is provided on a side surface 4 only on a side toward the first main surface 3 so as to extend in a thickness direction of the side surface 4, wherein, in the side surface 4 having the notch 11, the boundary 7 between the groove surface 6 and the fracture surface 5 has first curved portions R1 on opposite sides of the notch 11, the first curved portions R1 being convex toward the first main surface 3 of the substrate main body kp in side view; and also has a second curved portion R2 on a second-main-surface side of the notch 11, the second curved portion R2 being convex toward the second main surface (front surface) 2 of the substrate main body kp in side view.

公开(公告)号：EP2701469A4

公开(公告)日：2015-03-18

申请号：EP12773834

申请日：2012-02-01

Applicant: NGK SPARK PLUG CO

Inventor： HASEGAWA MASAMI ,  HIRAYAMA SATOSHI ,  KITO NAOKI

IPC: H05K1/02 ,  H05K3/00

CPC classification number: H05K1/0298 ,  H05K1/0306 ,  H05K3/0029 ,  H05K3/0052 ,  H05K3/403 ,  H05K3/46 ,  H05K2201/0909 ,  H05K2201/09154 ,  H05K2201/09181 ,  H05K2203/0346 ,  Y10T29/49155

Abstract: Provided are a ceramic wiring substrate having few burrs in the vicinity of a notch provided on a side surface of a substrate main body, in which a conductor layer provided on the inner wall of the notch exhibits excellent solderability; a multi-piece ceramic wiring substrate array for providing a plurality of the wiring substrates; and a method for reliably producing the wiring substrate array. The ceramic wiring substrate 1a includes a substrate main body 2a which has a rectangular shape in plan view, and which has a front surface 3 and a back surface 4 and has side surfaces 5, each being located between the front surface 3 and the back surface 4, and having a groove surface 8a located on a side toward the front surface 3 and a fracture surface 7 located on a side toward the back surface 4; and a notch 6 which has a concave shape in plan view, and which is provided on at least one of the side surfaces 5 so as to extend between the front surface 3 and the back surface 4, wherein, in the side surface 5 having the notch 6, the boundary 11 between the groove surface 8a and the fracture surface 7 has curved portions 11r on opposite sides of the notch 6, the curved portions 11r being convex toward the front surface 3 of the substrate main body 2a in side view.

公开(公告)号：EP2286468A4

公开(公告)日：2013-11-06

申请号：EP09743402

申请日：2009-05-04

Applicant: DIALIGHT CORP

Inventor： OESTERHELD KLAUS ,  JENKINS KENNETH

IPC: H05K1/14 ,  H05K3/36

CPC classification number: F21K9/20 ,  F21K9/30 ,  F21W2111/00 ,  H05K1/141 ,  H05K1/181 ,  H05K3/366 ,  H05K2201/049 ,  H05K2201/09181 ,  H05K2201/10106

Abstract: The present invention is directed to a surface mount circuit board indicator. In one embodiment the surface mount circuit board indicator includes a printed circuit board (PCB) having at least one light emitting diode (LED) die, one or more traces and at least one lens, a housing comprising at least one opening on a side along a perimeter of the housing, wherein the PCB is coupled to the housing such that a light output surface of the at least one LED die faces a same direction as the at least one opening and at least one alignment pin coupled to the housing.

Abstract translation: 本发明涉及一种表面贴装电路板指示器。 在一个实施例中，表面贴装电路板指示器包括具有至少一个发光二极管（LED）裸片，一个或多个迹线和至少一个透镜的印刷电路板（PCB），壳体包括沿着一侧的至少一个开口 壳体的周边，其中PCB耦合到壳体，使得至少一个LED管芯的光输出表面面向与至少一个开口相同的方向，以及耦合到壳体的至少一个对准销。

公开(公告)号：EP2286468A1

公开(公告)日：2011-02-23

申请号：EP09743402.1

申请日：2009-05-04

Applicant: Dialight Corporation

Inventor： OESTERHELD, Klaus ,  JENKINS, Kenneth

IPC: H01L33/00

CPC classification number: F21K9/20 ,  F21W2111/00 ,  H05K1/141 ,  H05K1/181 ,  H05K3/366 ,  H05K2201/049 ,  H05K2201/09181 ,  H05K2201/10106

Abstract: The present invention is directed to a surface mount circuit board indicator. In one embodiment the surface mount circuit board indicator includes a printed circuit board (PCB) having at least one light emitting diode (LED) die, one or more traces and at least one lens, a housing comprising at least one opening on a side along a perimeter of the housing, wherein the PCB is coupled to the housing such that a light output surface of the at least one LED die faces a same direction as the at least one opening and at least one alignment pin coupled to the housing.

公开(公告)号：EP1724832A3

公开(公告)日：2010-09-01

申请号：EP06010226.6

申请日：2006-05-18

Applicant: Panasonic Corporation

Inventor： Kimura,Junichi c/o Matsushita Elec. Ind. Co.,Ltd ,  Honjo,Kazuhiko c/o Matsushita Elec. Ind. Co.,Ltd ,  Kawamoto, Eiji c/o Matsushita Elec. Ind. Co., Ltd. ,  Harada, Shinji c/o Matsushita Elec. Ind. Co., Ltd. ,  Kitagawa, Motoyoshi Matsushita Elec. Ind. Co.,Ltd.

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/10 ,  H01L25/065

CPC classification number: H05K1/144 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/1627 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0237 ,  H05K1/185 ,  H05K3/0052 ,  H05K3/3436 ,  H05K3/403 ,  H05K3/42 ,  H05K2201/09181 ,  H05K2201/10371 ,  H05K2201/10666 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: A multilayer module which includes parts-containing module (32) whose circuit board (1) has been mounted at one surface with electronic component (2a) and the electronic component is covered with resin layer (39). Connection terminals (34a), (34b) have been provided either at resin layer (39) or at the other surface of circuit board (1), also through hole (46) has been provided for connection between the two surfaces of module (32). Also included is module (33), which has been provided with connection terminal (35a), (35b) at a place corresponding to connection terminal (34a), (34b), and through hole (47) for connection between the connection terminal (35a), (35b) and electronic component (2b). Disposed between conductor layer (34) and conductor layer (35) is insulation layer (36), which insulation layer having conductive bond (37) for connection between connection terminals (34a), (34b) and connection terminals (35a), (35b), respectively. In the above-described configuration, places of through hole (47) and electronic component (2b) in module (33) are not restricted by a location of through hole (46).

公开(公告)号：EP1570496B1

公开(公告)日：2008-05-14

申请号：EP03721372.5

申请日：2003-03-14

Applicant: Bourns, Inc.

Inventor： BURKE, Ray ,  O'BRIEN, Maurice ,  LAN, Poting ,  CHU, Stelar

IPC: H01C1/14 ,  H01C7/02

CPC classification number: H01C7/027 ,  H01C1/1406 ,  H01C1/148 ,  H01C7/02 ,  H01C17/28 ,  H05K1/0206 ,  H05K1/056 ,  H05K3/0052 ,  H05K3/403 ,  H05K3/429 ,  H05K3/44 ,  H05K3/445 ,  H05K2201/09181 ,  H05K2201/09554 ,  H05K2201/09845

Abstract: An electronic device is manufactured using printed circuit board manufacturing processes. In particular, a laminar device comprises a first metal layer (12), a second metal layer (14), at least one layer of device material sandwiched between the first and second metal layers. A first layer of insulating material (40) substantially covers the first metal layer (12). A third metal layer (48) is provided on the first layer of insulating material (40). This third metal layer (48) is divided to provide a first terminal (90) and a second terminal (92). The first terminal (90) is electrically connected to the first metal layer (12) by a conductive interconnect (84) formed through said first layer of insulating material (40), and the second terminal (92) is electrically connected to said second metal layer (14) by a conductive path (68) comprising an insulated conductive channel which passes through and is insulated from said first metal layer (12) and said at least one layer of device material (16). The use of an insulated channel provides a cost effective method of manufacture and maximizes the effective area of device material used. A PTC component is built through this method.

公开(公告)号：EP1662778B1

公开(公告)日：2008-03-05

申请号：EP05257354.0

申请日：2005-11-30

Applicant: Psion Teklogix Systems Inc.

Inventor： Kricorissian, Gregg ,  Zhang, Tao

IPC: H04N5/225 ,  H05K1/14

CPC classification number: H04N5/2253 ,  H04N5/2256 ,  H05K1/116 ,  H05K1/144 ,  H05K3/3405 ,  H05K3/366 ,  H05K3/368 ,  H05K3/403 ,  H05K2201/048 ,  H05K2201/09145 ,  H05K2201/09181 ,  H05K2201/09481 ,  H05K2201/10287 ,  H05K2201/2072 ,  H05K2203/128 ,  Y10T29/49144 ,  Y10T29/49169

公开(公告)号：EP0720232B1

公开(公告)日：2007-04-11

申请号：EP94927045.8

申请日：1994-09-14

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： YAMAGUCHI, Masayoshi 2-22, Nishimachi 1-chome ,  SAWANO, Mitsutoshi 13-23, Soshigaya 3-chome ,  HOHKI, Kazutoshi 20-6, Higashi-Toyoda 3-chome

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/16 ,  H01L23/538

CPC classification number: H01L25/50 ,  H01L23/24 ,  H01L23/5385 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/16 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  H05K1/141 ,  H05K1/147 ,  H05K3/3442 ,  H05K3/368 ,  H05K3/4614 ,  H05K3/4623 ,  H05K2201/09181 ,  H05K2201/09536 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Bare chips (201 to 203) are mounted on regions (101 to 103) of a printed wiring board (100), respectively. The chips are soldered to a motherboard at external electrode pads (105) on their borders. Lead pads (107) and the external electrode pads (105) are interconnected through a circuit pattern (109), through-holes (111) and interstitial via-holes (112). A circuit pattern (109) is disposed on a die bonding surface of the bare IC chips (201, 202) for which insulation is not necessary. A multi-chip module is thus completed.

公开(公告)号：EP1729555A1

公开(公告)日：2006-12-06

申请号：EP05011726.6

申请日：2005-05-31

Applicant: SIEMENS AKTIENGESELLSCHAFT

Inventor： Fischer, Alfred ,  Gubisch, Thomas ,  Niebler, Günther ,  Teichrieb, Eugen

IPC: H05K3/36 ,  H05K1/14

CPC classification number: H05K3/366 ,  H05K3/0044 ,  H05K3/403 ,  H05K2201/048 ,  H05K2201/09036 ,  H05K2201/09181 ,  H05K2201/09645 ,  H05K2203/1476

Abstract: Bei dem Verfahren zur Herstellung einer ersten Leiterplatte (1) zur Aufnahme einer weiteren Leiterplatte (20) werden Kontaktierungsflächen (11 - 14) auf der ersten Leiterplatte (1) aufgebracht. Es wird eine schlitzförmige Öffnung (4) mit seitlichen Ausbuchtungen (7) in die erste Leiterplatte im Bereich der Kontaktierungsflächen (11-14) eingebracht, um eine Klemmleiste (25) der weiteren Leiterplatte (20) aufnehmen zu können. Die Innenseite (5) der schlitzförmigen Öffnung (4) wird mit einer leitfähigen Schicht (52) überzogen, so dass eine elektrische Verbindung mit den Kontaktierungsflächen (11 - 14) hergestellt wird. Die schlitzförmige Öffnung (9) wird soweit verbreitert, dass die leitfähige Schicht (52) nur noch in den Ausbuchtungen (7) enthalten ist. In einem alternativen Herstellungsverfahren wird anstelle einer Öffnung (4) eine Vertiefung (4') in eine zweite Leiterplatte (1') eingebracht. Dadurch kann die schlitzförmige Vertiefung (4') mit den seitlichen Ausbuchtungen (7) vorteilhaft in einem Arbeitsgang hergestellt werden. Die Vielzahl von Bohrungen zum Erhalt der Vielzahl von Löchern entfällt. Die Erfindung betrifft ferner Herstellungsverfahren für ein Leiterplattensystem sowie durch das Verfahren hergestellte Leiterplatten und Leiterplattensysteme.

Abstract translation: 该方法涉及形成在用于接收另一印刷电路板的端子条接触表面（11-14）的区域中的槽状的开口（4）具有横向突起（7）插入的印刷电路板英寸 开口的内侧涂覆有导电层上的电连接也是如此与所述表面制成。 开口变宽，求DASS模层中的突起被接收。 因此独立claimsoft包括用于印刷电路板系统，其包括印刷电路板。