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2671 条记录 (耗时 0.026 秒)

    COMMUNICATION DEVICE AND MANUFACTURING METHOD THEREOF
    61.
    发明公开
    COMMUNICATION DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：EP4191648A1

    公开(公告)日：2023-06-07

    申请号：EP22210997.7

    申请日：2022-12-02

    申请人： InnoLux Corporation

    发明人： LIN, Jia-Sin ,  FANG, Wen-Chi ,  CHI, Jen-Hai ,  HUANG, Zhi-Fu ,  CHEN, Pei-Chi ,  TSAI, Wan-Chun

    IPC分类号： H01L21/683 ,  H01L23/538 ,  H01L23/66 ,  H01L25/16 ,  H01L25/18 ,  H01L25/00 ,  H01L25/065

    摘要： This disclosure provides a communication device and a manufacturing method thereof. The manufacturing method of the communication device includes the following steps: providing a first dielectric layer, wherein the first dielectric layer includes a first region and a second region, and the first dielectric layer has a first surface and a second surface opposite to the first surface; providing a second dielectric layer; combining the first dielectric layer and the second dielectric layer with a sealing element, so that the sealing element is disposed between the first surface of the first dielectric layer and a third surface of the second dielectric layer; after combining the first dielectric layer and the second dielectric layer, thinning the second surface of the first dielectric layer; and disposing a first communication element on the first surface of the first dielectric layer in the first region.

    ELECTRONIC DEVICE AND MANUFACTURING METHOD OF ELECTRONIC DEVICE
    67.
    发明公开
    ELECTRONIC DEVICE AND MANUFACTURING METHOD OF ELECTRONIC DEVICE 审中-公开

    公开(公告)号：EP4141916A1

    公开(公告)日：2023-03-01

    申请号：EP22187736.8

    申请日：2022-07-29

    申请人： InnoLux Corporation

    发明人： HU, Shun-Yuan ,  HO, Chia-Chi

    IPC分类号： H01L21/683 ,  H01L23/66 ,  H01L25/16 ,  H01L25/065 ,  H01L21/60 ,  H01L23/00 ,  H01L23/04 ,  H01L21/56 ,  H01L33/54

    摘要： Disclosed are an electronic device (100) and a manufacturing method of an electronic device (100). The manufacturing method includes the following. A first substrate (10,10') is provided. The first substrate (10,10') includes a plurality of chips (110). A second substrate (20) is provided. A transfer process is performed to sequentially transfer a first chip (112) and a second chip (114) among the chips (110) to the second substrate (20). The second chip (114) is adjacent to the first chip (112). A first angle (Al) is between a first extension direction (D1) of a first side (S1) of the first chip (112) and an extension direction (D) of a first boundary (B) of the second substrate (20). A second angle (A2) is between a second extension direction (D2) of a second side (S2) of the second chip (114) and the extension direction (D) of the first boundary (B) of the second substrate (20). The first angle (Al) is different from the second angle (A2).

    VERTICAL MEMORY DEVICE
    68.
    发明公开
    VERTICAL MEMORY DEVICE 审中-公开

    公开(公告)号：EP4105992A3

    公开(公告)日：2023-02-08

    申请号：EP22178985.2

    申请日：2022-06-14

    申请人： Samsung Electronics Co., Ltd.

    发明人： KWON, Yongseok ,  RHO, Youngsik ,  PARK, Sangwon ,  SEO, Sungwhan ,  LEE, Dongkyu ,  JEONG, Jaeyong

    IPC分类号： H01L27/11578 ,  H01L27/11526 ,  H01L25/065 ,  H01L23/00 ,  H01L49/02

    摘要： A memory device including a first substrate extending in a first direction and a second direction perpendicular to the first direction, the first substrate including a memory cell region and a first peripheral circuit region, and a second substrate, including a second peripheral circuit region, extending in the first and second direction, the second substrate overlapping the first substrate in a third direction perpendicular to the first and second direction. The memory device also including a memory cell array disposed in the memory cell region and including a plurality of vertical channel structures extending in the third direction, a peripheral circuit disposed in the second peripheral circuit region, and a resistor extending in the third direction through the first peripheral circuit region and the second peripheral circuit region. The resistor including a plurality of resistance contact structures overlapping the plurality of vertical channel structures in the first direction.

    CHIP PACKAGE ASSEMBLY AND ELECTRONIC DEVICE COMPRISING THE CHIP PACKAGE ASSEMBLY
    69.
    发明公开
    CHIP PACKAGE ASSEMBLY AND ELECTRONIC DEVICE COMPRISING THE CHIP PACKAGE ASSEMBLY 审中-公开

    公开(公告)号：EP4125115A1

    公开(公告)日：2023-02-01

    申请号：EP22186640.3

    申请日：2022-07-25

    申请人： Huawei Technologies Co., Ltd.

    发明人： PENG, Hao ,  LIAO, Xiaojing ,  HOU, Zhaozheng

    IPC分类号： H01L21/48 ,  H01L23/13 ,  H01L23/14 ,  H01L23/538 ,  H01L23/552 ,  H01L23/367 ,  H01L25/065 ,  H01L25/00

    摘要： This application discloses a chip package assembly, an electronic device, and a preparation method of a chip package assembly. The chip package assembly includes a package substrate, a chip, and a heat dissipation part. The package substrate includes an upper conductive layer, a lower conductive layer, and a conductive part connected between the upper conductive layer and the lower conductive layer. The chip includes a front electrode and a back electrode that are disposed opposite to each other, the chip is embedded in the package substrate, the conductive part surrounds the chip, the front electrode is connected to the lower conductive layer, and the back electrode is connected to the upper conductive layer. The heat dissipation part is connected to a surface of the upper conductive layer that is away from the chip. The upper conductive layer, the lower conductive layer, and the conductive part each have a heat-conducting property. In this application, the chip is connected to the upper conductive layer and the lower conductive layer of the package substrate, so that heat generated by the chip can be bidirectionally conducted for heat dissipation. Further, the heat dissipation part is disposed on the upper conductive layer, so that the chip package assembly can achieve a better heat dissipation effect.