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    Plasma etching of polymer materials
    71.
    发明公开
    Plasma etching of polymer materials 审中-公开
    Plasmaätzenvon Polymermaterialien

    公开(公告)号：EP0997929A1

    公开(公告)日：2000-05-03

    申请号：EP98402724.3

    申请日：1998-10-30

    申请人： Tokyo Electron Limited ,  COMMISSARIAT A L'ENERGIE ATOMIQUE

    发明人： Vivensang, Christophe P. ,  Vinet, Françoise

    IPC分类号： H01L21/311 ,  H01L21/312

    CPC分类号： H01L21/31144 ,  H01L21/02118 ,  H01L21/31138 ,  H01L21/3121

    摘要： A mineral material layer and a photoresist polymer material layer are successively formed on a polymer material (6) supported by a substrate (5). The photoresist polymer material layer is patterned by way of lithography, and the pattern thus defined is transferred to the mineral material layer in order to form a hard mask (7a). The polymer material (6) is then dry etched using a plasma generated from a gas mixture comprising sulphur dioxide (SO 2 ), oxygen (O 2 ) and argon (Ar). The use of sulphur dioxide enables to carry out anisotropic etching in the polymer material (6). Further a good etching selectivity can be achieved thanks to the hard mask (7a).

    摘要翻译： 在由基板（5）支撑的聚合物材料（6）上依次形成矿物层和光致抗蚀剂聚合物材料层。 通过光刻法将光致抗蚀剂聚合物材料层图案化，并且将如此限定的图案转移到矿物材料层以形成硬掩模（7a）。 然后使用由包含二氧化硫（SO 2），氧（O 2）和氩（Ar）的气体混合物产生的等离子体对聚合物材料（6）进行干蚀刻。 使用二氧化硫能够在聚合物材料（6）中进行各向异性蚀刻。 此外，由于硬掩模（7a），可以实现良好的蚀刻选择性。

    PROCESS FOR THE PRODUCTION OF SEMICONDUCTOR DEVICE
    73.
    发明公开
    PROCESS FOR THE PRODUCTION OF SEMICONDUCTOR DEVICE 失效
    生产半导体器件的方法

    公开(公告)号：EP0933802A1

    公开(公告)日：1999-08-04

    申请号：EP97911513.6

    申请日：1997-11-11

    申请人： TOKYO ELECTRON LIMITED

    发明人： AKAHORI, Takashi ,  ISHIZUKA, Shuichi, 202, Shiroyama New Heights ,  ENDO, Shunichi ,  AOKI, Takeshi ,  HIRATA, Tadashi, 1004, Dragon Mansion

    IPC分类号： H01L21/3065

    CPC分类号： H01L21/31144 ,  H01L21/31138 ,  H01L21/76802 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： It is an object of the present invention to provide a process for a fluorine containing carbon film (a CF film), which can put an interlayer insulator film of a fluorine containing carbon film into practice.
    A conductive film, e.g., a TiN film 41, is formed on a CF film 4. After a pattern of a resist film 42 is formed thereon, the TiN film 41 is etched with, e.g., BCl 3 gas. Thereafter, when the surface of the wafer is irradiated with O 2 plasma, the CF film is chemically etched, and the resist film 42 is also etched. However, since the TiN film 41 functions as a mask, a predetermined hole can be formed. Although an interconnection layer of aluminum or the like is formed on the surface of the CF film 4, the TiN film 41 functions as an adhesion layer for adhering the interconnection layer to the CF film 4 and serves as a part of the interconnection layer. As the mask, an insulator film of SiO 2 or the like may be substituted for the conductive film.

    摘要翻译： 本发明的一个目的是提供一种含氟碳膜（CF膜）的方法，该方法可以实施含氟碳膜的层间绝缘膜。 在CF膜4上形成导电膜例如TiN膜41.在其上形成抗蚀剂膜42的图案之后，用例如BCl 3气体对TiN膜41进行蚀刻。 之后，当用O2等离子体照射晶片的表面时，CF膜被化学蚀刻，并且抗蚀剂膜42也被蚀刻。 但是，由于TiN膜41用作掩模，所以可以形成预定的孔。 尽管在CF膜4的表面上形成了铝等的互连层，但是TiN膜41用作用于将互连层粘附到CF膜4并且用作互连层的一部分的粘附层。 作为掩模，可以用SiO 2等的绝缘膜代替导电膜。

    High speed ashing method
    77.
    发明公开
    High speed ashing method 失效
    Hochgeschwindigkeitsverfahren zur Veraschung von Photolack

    公开(公告)号：EP0740333A2

    公开(公告)日：1996-10-30

    申请号：EP96106139.7

    申请日：1996-04-18

    申请人： NEC CORPORATION

    发明人： Kawamoto, Hideaki

    IPC分类号： H01L21/311 ,  H01L21/321

    CPC分类号： H01L21/02071 ,  G03F7/427 ,  H01L21/31138

    摘要： A wafer (11) is conveyed in a vacuum from an Al etching chamber after the Al etching and is fed into an ashing chamber (15) without coming into contact with the atmosphere. After the wafer (11) was conveyed, CH 3 OH gas of 200 sccm is first introduced by a valve (30a) and a pressure is adjusted to 1.2 Torr. Subsequently, a microwave current of 450 mA is supplied, thereby forming a plasma. The wafer (11) is processed by a down-flow system of a CH 3 OH plasma. The supply of the CH 3 OH gas is stopped by closing the valve (30a). Next, oxygen gas of 400 sccm is introduced by opening a valve (30b). A microwave current of 450 mA is supplied at a pressure of 1.2 Torr, thereby forming a plasma. A resist on the wafer 11 is ashed and eliminated by a down-flow process of an oxygen plasma. By those processes, the corrosion prevention and the resist ashing can be perfectly executed.

    摘要翻译： 在Al蚀刻之后，晶片（11）在真空中从Al蚀刻室输送，并且进入灰化室（15）而不与大气接触。 在输送晶片（11）之后，首先通过阀（30a）引入200sccm的CH 3 OH气体，并将压力调节至1.2Torr。 随后，提供450mA的微波电流，从而形成等离子体。 晶片（11）由CH3OH等离子体的下流系统处理。 通过关闭阀（30a）来停止供应CH 3 OH气体。 接下来，通过打开阀（30b）引入400sccm的氧气。 在1.2Torr的压力下供给450mA的微波电流，从而形成等离子体。 通过氧等离子体的下流过程，将晶片11上的抗蚀剂灰化并消除。 通过这些工艺，可以完美地执行防腐蚀和抗蚀剂灰化。

    Anisotropic plasma etching of semiconductor device
    78.
    发明公开
    Anisotropic plasma etching of semiconductor device 失效
    半导体器件的各向异性等离子体蚀刻。

    公开(公告)号：EP0683512A2

    公开(公告)日：1995-11-22

    申请号：EP95106830.3

    申请日：1995-05-05

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Jeng, Shin-puu

    IPC分类号： H01L21/311

    CPC分类号： H01L21/31138 ,  G03F7/427

    摘要： This invention encompasses using anisotropic plasma at a low temperature to strip resist from a semiconductor wafer. A semiconductor wafer 10 is placed in a reactor 26 which contains an oxygen plasma source 28 . The oxygen plasma source 28 emits oxygen plasma 32 which is drawn towards the biased wafer 10 , exposing the resist layer 22 of the wafer to anisotropic oxygen plasma. A sensor 30 detects when the ashing of the resist is complete, and then the plasma source is turned off.
    Advantages of the invention include the ability to remove resist from wafers without damaging polymeric dielectric layers, which are sensitive to the harsh effects of traditional resist removal methods. With the present invention, very little damage occurs to the material on the sidewalls of vias.

    Method for fabricating tungsten local interconnections in high density CMOS circuits
    79.
    发明公开
    Method for fabricating tungsten local interconnections in high density CMOS circuits 失效
    赫斯特伦·弗兰克·冯·洛卡伦·Wolframverbindungen在CMOS-Schaltungen von hoher Dichte。

    公开(公告)号：EP0613177A2

    公开(公告)日：1994-08-31

    申请号：EP94100576.1

    申请日：1994-01-17

    申请人： International Business Machines Corporation

    发明人： Kobeda,Edward ,  Gambino, Jeffrey Peter ,  Gifford, George Gordon ,  Mazzeo, Nickolas Joseph

    IPC分类号： H01L21/90 ,  H01L21/321

    CPC分类号： H01L21/32136 ,  H01L21/31138 ,  H01L21/76895 ,  Y10S438/97

    摘要： An etch stop layer of chromium (24) is initially deposited on the circuit elements of the CMOS silicon substrate. Next, a conductive layer of tungsten (26) is non-selectively deposited on the chromium layer (24). A photoresist mask (28) is then lithographically patterned over the tungsten layer (26). The tungsten layer (26) is then etched down to, and stopping at, the chromium layer (24), after which the photoresist mask (28) is stripped. The stripping preferably uses a low temperature plasma etch in O₂ at a temperature of less than 100°C. Finally, a directional O₂ reactive ion etch is used to remove the chromium layer (24) selectively to the silicon substrate.

    摘要翻译： 本发明提供了一种用于在高密度CMOS电路中制造钨局部互连的方法，并且还提供了具有由钨形成的局部互连的高密度CMOS电路。 根据该方法，最初在CMOS硅衬底的电路元件上沉积铬的蚀刻停止层。 接下来，在铬层上不选择性地沉积钨的导电层。 然后光致抗蚀剂掩模在钨层上被光刻图案化。 然后将钨层蚀刻到铬层上并停止在其上，之后剥离光致抗蚀剂掩模。 剥离优选在低于100℃的温度下在O 2中使用低温等离子体蚀刻。最后，使用定向O 2反应离子蚀刻来选择性地去除硅衬底上的铬层。 借助于钨局部互连层下方的铬蚀刻停止层形成无边界触点。 该方法的整合方法导致使用标准光刻胶掩模在地形图上形成的各向异性金属线。 这种方法还允许触点的部分重叠以减小器件尺寸，从而导致改善的密度和性能。