公开(公告)号：EP3347769A1

公开(公告)日：2018-07-18

申请号：EP16763794.1

申请日：2016-09-09

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： POSSEME, Nicolas ,  SARRAZIN, Aurélien

IPC分类号： G03F7/00

CPC分类号： H01L21/31138 ,  B81C1/00031 ,  B81C2201/0149 ,  G03F7/0002 ,  H01L21/02115 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3086

摘要： The invention relates to a method for etching an assembled block copolymer layer comprising first and second polymer phases, in which the etching method includes exposing the assembled block copolymer layer to a plasma so as to etch the first polymer phase and simultaneously to deposit a carbon layer on the second polymer phase, the etching method being characterised in that the plasma is formed from a gas mixture comprising a depolymerising gas (Z) and an etching gas selected among the hydrocarbons (C
x H
y ).

公开(公告)号：EP3185287A4

公开(公告)日：2018-04-11

申请号：EP14881396

申请日：2014-10-27

申请人： BOE TECHNOLOGY GROUP CO LTD ,  BEIJING BOE OPTOELECTRONICS TECH CO LTD

发明人： JIANG XIAOHUI ,  YAN CHANGJIANG ,  ZHANG JIAXIANG

IPC分类号： H01L27/12 ,  H01L21/311

CPC分类号： H01L27/1248 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76816 ,  H01L21/77 ,  H01L27/12 ,  H01L27/1244 ,  H01L27/1262 ,  Y02P80/30

摘要： An array substrate, a manufacturing method thereof and a display device are disclosed. The array substrate comprises: a base substrate (1), thin-film transistors (TFTs), an isolation layer (10) and an organic resin layer (8) formed on the base substrate (1), and a common electrode layer (12) formed on the organic resin layer (8). The isolation layer (10) covers source electrodes (6) and drain electrodes (7) of the TFTs; the organic resin layer (8) covers the isolation layer (10) and is provided with first through holes (9) corresponding to the drain electrodes (7) of the TFTs; the isolation layer (10) is provided with second through holes (11) communicated with the first through holes (9) to expose partial drain electrodes (7); and the dimension of the second through holes (11) is greater than that of the first through holes (9). The array substrate, the manufacturing method thereof and the display device resolve the problem of forming dark dots, ensure the product quality, reduce the waste of production materials, and reduce the production cost.

公开(公告)号：EP3213343A1

公开(公告)日：2017-09-06

申请号：EP15791164.5

申请日：2015-10-27

申请人： Microchip Technology Incorporated

发明人： SATO, Justin Hiroki ,  STOM, Gregory Allen

IPC分类号： H01L21/762 ,  H01L21/3105

CPC分类号： H01L21/76224 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02238 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/30604 ,  H01L21/31051 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76202 ,  H01L29/0649

摘要： A layer of partially planarized organosilicate (DUO) is spin-coated onto a layer of high density plasma (HDP) oxide on a silicon wafer after the shallow trench isolation (STI) is filled with the HDP oxide. Then the DUO layer is etched using a specialized process specifically tuned to etch the DUO and high density plasma (HDP) oxide at a certain selectivity. The higher areas of the wafer topography (active Si areas) have thinner DUO and as the etch process proceeds it starts to etch through the HDP oxide in these areas (active Si areas). The etch process is stopped after a certain depth is reached and before touching down on the silicon nitride oxidation layer. The DUO is removed and a standard chemical-mechanical polish (CMP) is performed on the silicon wafer. After the CMP step the silicon nitride is removed, exposing the silicon substrate between the field oxides.

摘要翻译： 在用HDP氧化物填充浅沟槽隔离（STI）之后，将部分平面化的有机硅酸盐（DUO）层旋涂到硅晶片上的高密度等离子体（HDP）氧化物层上。 然后使用专门调整的特定工艺蚀刻DUO层，以一定选择性蚀刻DUO和高密度等离子体（HDP）氧化物。 晶圆形貌（有源硅区域）的较高区域具有较薄的DUO，随着蚀刻工艺的进行，它开始蚀刻这些区域（活性Si区域）中的HDP氧化物。 蚀刻过程在达到一定深度后并在接触氮化硅氧化层之前停止。 DUO被移除并且在硅晶片上执行标准的化学机械抛光（CMP）。 在CMP步骤之后，去除氮化硅，暴露场氧化物之间的硅衬底。

公开(公告)号：EP3040777A4

公开(公告)日：2017-04-19

申请号：EP14840214

申请日：2014-08-27

申请人： NISSAN CHEMICAL IND LTD

发明人： OHASHI TOMOYA ,  KIMURA SHIGEO ,  USUI YUKI ,  OGATA HIROTO

IPC分类号： G03F7/038 ,  C08F8/14 ,  C08F20/32 ,  G03F7/11 ,  G03F7/26 ,  G03F7/40 ,  H01L21/027

CPC分类号： H01L21/3086 ,  C08F8/14 ,  C08F220/32 ,  G03F7/038 ,  G03F7/094 ,  G03F7/40 ,  H01L21/0273 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31138 ,  H01L21/31144 ,  C08F220/26 ,  C08F220/14 ,  C08F220/18

摘要： The present invention provides a pattern forming method which uses a resist underlayer film having resistance to a basic aqueous hydrogen peroxide solution. A pattern forming method comprising: a first step of applying a resist underlayer film-forming composition containing a solvent and a polymer having a weight average molecular weight of 1,000 to 100,000 and an epoxy group on a semiconductor substrate that may have an inorganic film on the surface, followed by baking, to form a resist underlayer film; a second step of forming a resist pattern on the resist underlayer film; a third step of dry etching the resist underlayer film using the resist pattern as a mask to expose a surface of the inorganic film or the semiconductor substrate; and a forth step of wet etching the inorganic film or the semiconductor substrate using the dry-etched resist underlayer film as a mask and a basic aqueous hydrogen peroxide solution.

摘要翻译： 本发明提供了使用对碱性过氧化氢水溶液具有耐性的抗蚀剂下层膜的图案形成方法。 一种图案形成方法，包括：第一步骤，将含有溶剂的重均分子量为1,000〜100,000的抗蚀剂下层膜形成组合物和环氧基涂布在可以具有无机膜的半导体衬底上 表面，然后烘烤，形成抗蚀剂下层膜; 在抗蚀剂下层膜上形成抗蚀剂图案的第二步骤; 使用抗蚀剂图案作为掩模来干蚀刻抗蚀剂下层膜以暴露无机膜或半导体衬底的表面的第三步骤; 以及使用干蚀刻抗蚀剂下层膜作为掩模和碱性过氧化氢水溶液湿法蚀刻无机膜或半导体衬底的第四步骤。

公开(公告)号：EP2166564B1

公开(公告)日：2017-04-12

申请号：EP09170481.7

申请日：2009-09-16

申请人： IMEC

发明人： Le, Quoc Toan ,  Kesters, Els ,  Vereecke, Guy

IPC分类号： H01L21/311 ,  G03F7/42

CPC分类号： H01L21/31138 ,  G03F7/427 ,  H01L21/31133

公开(公告)号：EP2981985A4

公开(公告)日：2016-11-02

申请号：EP14779168

申请日：2014-04-01

申请人： BREWER SCIENCE INC

发明人： XU KUI ,  HOCKEY MARY ANN ,  GUERRERO DOUGLAS

IPC分类号： H01L21/027 ,  C08L33/12

CPC分类号： H01L21/0331 ,  B81C1/00031 ,  B81C2201/0149 ,  C08F212/08 ,  C08F212/32 ,  C08F293/005 ,  C08F2438/03 ,  C08L33/12 ,  C09D125/08 ,  C09D125/14 ,  C09D125/16 ,  C09D153/00 ,  G03F7/0002 ,  H01L21/0337 ,  H01L21/31133 ,  H01L21/31138

公开(公告)号：EP2975633A4

公开(公告)日：2016-10-26

申请号：EP14785929

申请日：2014-04-09

申请人： TOKYO ELECTRON LTD

发明人： MORIKITA SHINYA ,  NISHIMURA EIICHI ,  YAMASHITA FUMIKO

IPC分类号： H01L21/311 ,  H01L21/027

CPC分类号： H01L21/31133 ,  B81C1/00031 ,  B81C2201/0149 ,  G03F7/0002 ,  H01J37/32091 ,  H01J37/32577 ,  H01L21/02118 ,  H01L21/02351 ,  H01L21/0271 ,  H01L21/31138 ,  H01L21/31144

摘要： A pattern is formed on an underlying layer of a target object by a pattern forming method. The pattern forming method includes (a) forming a block copolymer layer, which includes a first polymer and a second polymer and is configured to be self-assembled, on the underlying layer; (b) processing the target object to form a first region containing the first polymer and a second region containing the second polymer in the block copolymer layer; (c) etching the second region partway in a thickness direction of the second region in a capacitively coupled plasma processing apparatus after the processing of the target object; (d) generating secondary electrons from an upper electrode of the plasma processing apparatus by applying a negative DC voltage to the upper electrode and irradiating the secondary electrons onto the target object, after the etching of the second region; and (e) additionally etching the second region in the plasma processing apparatus after the irradiating of the secondary electrons onto the target object.

公开(公告)号：EP2881794A4

公开(公告)日：2016-05-04

申请号：EP13825237

申请日：2013-07-29

申请人： NISSAN CHEMICAL IND LTD

发明人： SHIBAYAMA WATARU ,  SHIGAKI SHUHEI ,  SAKAMOTO RIKIMARU

IPC分类号： G03F7/11 ,  C08K5/42 ,  G03F7/004 ,  G03F7/075 ,  G03F7/09 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/311

CPC分类号： C08K5/42 ,  C09D183/04 ,  G03F7/0045 ,  G03F7/0752 ,  G03F7/0755 ,  G03F7/0757 ,  G03F7/094 ,  G03F7/11 ,  H01L21/3105 ,  H01L21/31138 ,  H01L21/31144 ,  C08K5/092

摘要： There is provided a resist underlayer film-forming composition for EUV lithography which shows good resist shape. A resist underlayer film-forming composition for EUV lithography, comprising: a hydrolyzable organosilane, a hydrolyzed product thereof, or a hydrolyzed condensate thereof, as a silane; and a salt of a sulfonic acid ion containing a hydrocarbon group with an onium ion. The hydrolyzable organosilane preferably comprises at least one organic silicon compound selected from the group consisting of compounds of Formula (1): €ƒ€ƒ€ƒ€ƒ€ƒ€ƒ€ƒ€ƒR 1 a Si(R 2 ) 4-a €ƒ€ƒ€ƒ€ƒ€ƒFormula (1) and compounds of Formula (2): €ƒ€ƒ€ƒ€ƒ€ƒ€ƒ€ƒ€ƒ[R 3 c Si(R 4 ) 3-c ] 2 Y b €ƒ€ƒ€ƒ€ƒ€ƒFormula (2) a hydrolyzed product thereof, or a hydrolyzed condensate thereof. A method for manufacturing a semiconductor device, the method comprising: forming an organic underlayer film on a semiconductor substrate; forming a resist underlayer film by applying the resist underlayer film-forming composition onto the organic underlayer film, and then baking the applied resist underlayer film-forming composition; forming a resist film by applying a composition for EUV resists onto the resist underlayer film; EUV-exposing the resist film; and obtaining a resist pattern by developing the exposed resist film.

公开(公告)号：EP2975633A1

公开(公告)日：2016-01-20

申请号：EP14785929.2

申请日：2014-04-09

申请人： Tokyo Electron Limited

发明人： MORIKITA Shinya ,  NISHIMURA Eiichi ,  YAMASHITA Fumiko

IPC分类号： H01L21/3065 ,  H01L21/027 ,  H05H1/46

CPC分类号： H01L21/31133 ,  B81C1/00031 ,  B81C2201/0149 ,  G03F7/0002 ,  H01J37/32091 ,  H01J37/32577 ,  H01L21/02118 ,  H01L21/02351 ,  H01L21/0271 ,  H01L21/31138 ,  H01L21/31144

摘要： A pattern is formed on an underlying layer of a target object by a pattern forming method. The pattern forming method includes (a) forming a block copolymer layer, which includes a first polymer and a second polymer and is configured to be self-assembled, on the underlying layer; (b) processing the target object to form a first region containing the first polymer and a second region containing the second polymer in the block copolymer layer; (c) etching the second region partway in a thickness direction of the second region in a capacitively coupled plasma processing apparatus after the processing of the target object; (d) generating secondary electrons from an upper electrode of the plasma processing apparatus by applying a negative DC voltage to the upper electrode and irradiating the secondary electrons onto the target object, after the etching of the second region; and (e) additionally etching the second region in the plasma processing apparatus after the irradiating of the secondary electrons onto the target object.

摘要翻译： 通过图案形成方法在目标物体的下层上形成图案。 该图案形成方法包括：（a）在底层上形成包括第一聚合物和第二聚合物并被配置为自组装的嵌段共聚物层; （b）在所述嵌段共聚物层中处理所述目标物以形成包含所述第一聚合物的第一区域和包含所述第二聚合物的第二区域; （c）在目标物体的处理之后，在电容耦合等离子体处理装置中在第二区域的厚度方向的中途蚀刻第二区域; （d）在蚀刻所述第二区域之后，通过向所述上电极施加负DC电压并将所述二次电子照射到所述目标物体上从所述等离子体处理装置的上电极产生二次电子; 和（e）在将二次电子照射到目标物体上之后，另外蚀刻等离子体处理装置中的第二区域。

公开(公告)号：EP2828887A1

公开(公告)日：2015-01-28

申请号：EP13763857.3

申请日：2013-03-21

申请人： Tokyo Electron Limited

发明人： RANJAN, Alok ,  RALEY, Angelique

IPC分类号： H01L21/8238

CPC分类号： H01L21/0206 ,  H01J37/32082 ,  H01J2237/334 ,  H01L21/0212 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656

摘要： A method for performing a spacer etch process is described. The method includes providing a gate structure on a substrate having a low-k spacer material conformally applied over the gate structure, and performing a spacer etch process sequence to partially remove the spacer material from the gate structure and the substrate, while retaining a sidewall spacer positioned along a sidewall of the gate structure. The spacer etch process sequence may include depositing a spacer protection layer on an exposed surface of said spacer material, and performing one or more etching processes to selectively and anisotropically remove the spacer protection layer and the spacer material to leave behind the sidewall spacer on the sidewall of the gate structure, wherein, while being partly or fully consumed by the one or more etching processes, the spacer protection layer exhibits a reduced variation in composition and/or dielectric constant.

摘要翻译： 描述了一种用于执行间隔物蚀刻的工艺方法。 该方法包括在一个基片提供栅极结构，其具有共形地施加在栅结构上的低k间隔物材料;以及执行间隔物蚀刻工艺顺序以部分地从该栅极结构和基板除去所述间隔物材料，同时保持侧壁间隔物 沿着所述栅极结构的侧壁上的位置。 间隔物蚀刻工艺序列可以包括在所述间隔件材料的暴露表面上沉积间隔物的保护层，并进行一个或多个蚀刻工艺，以选择性和各向异性移除垫片保护层和间隔物材料的侧壁间隔物，以留下在侧壁 该栅极结构的，worin，同时被部分或完全地由一个或多个蚀刻工艺所消耗，间隔保护层表现出在组合物和/或介电常数的变化减小。