公开(公告)号：EP2395691A1

公开(公告)日：2011-12-14

申请号：EP09839613.8

申请日：2009-12-10

申请人： Panasonic Corporation

发明人： LI, Jifeng

IPC分类号： H04L1/00 ,  H03M13/35 ,  H04L1/16 ,  H04W28/04

CPC分类号： H04L1/0069 ,  H03M13/2957 ,  H03M13/6306 ,  H03M13/6362 ,  H04L1/0041 ,  H04L1/0059 ,  H04L1/1819

摘要： Disclosed is an encoding processing apparatus in which reception precision characteristics are improved by specially adapting puncture processing in respect of the code words for each encoding system. A puncture section (130) switches between a puncture pattern for a first code word partial sequence obtained on the basis of the head and tail in a fixed information block, and a puncture pattern for a second code word partial sequence obtained on the basis of the middle portion, excluding the head and tail. Also, the puncture section (130) receives the number of retransmissions of information from a retransmission control section (180) and switches the puncture pattern for the second code word partial sequence in accordance with the number of retransmissions. In addition, the puncture section (130) prioritising systematic bits over parity bits when puncturing the first code word partial sequence.

摘要翻译： 本发明公开了一种编码处理设备，其中通过针对每个编码系统针对码字专门适配打孔处理来提高接收精度特性。 删截单元（130）在基于固定信息块中的头部和尾部获得的第一码字部分序列的删余样式与基于第二码字部分序列获得的删余样式之间切换 中间部分，不包括头部和尾部。 此外，删截单元（130）接收来自重发控制单元（180）的重发次数，并根据重发次数切换第二码字部分序列的删余模式。 另外，当穿孔第一码字部分序列时，穿孔部分（130）将系统比特优先于奇偶比特。

公开(公告)号：EP2375667A1

公开(公告)日：2011-10-12

申请号：EP10184618.6

申请日：2004-10-15

申请人： FUJITSU LIMITED

发明人： Yano, Tetsuya ,  Obuchi, Kazuhisa ,  Miyazaki, Shunji

IPC分类号： H04L27/34

CPC分类号： H04L27/3488 ,  H03M13/25 ,  H03M13/2957 ,  H04L1/0041 ,  H04L1/0057 ,  H04L1/0067 ,  H04L1/16

摘要： A transmitting apparatus comprising circuitry operable to generate a plurality of bit sequences using bits included in a first data block and a second data block, circuitry operable to control the plurality of bit sequences to correspond to a signal point on the phase plane, comprising a bit sequence generating unit operable to control the generation of the bit sequences to adjust an occupation rate occupied with predetermined bits included in the first data block (CODE BLOCK 1) to be closer to an occupation rate occupied with predetermined bits included in the second data block (CODE BLOCK 2) in regard to bit positions of the predetermined bits, based on an error tolerance of the respective bit sequences generated resulting from the correspondence to a signal point on the phase plane, and circuitry operable to transmit the signals obtained by multi-level modulations in accordance with each signal point.

公开(公告)号：EP1594130B1

公开(公告)日：2011-09-28

申请号：EP03705157.0

申请日：2003-02-14

申请人： FUJITSU LIMITED

发明人： ITAKURA, Akihiro

IPC分类号： G11B20/10 ,  G11B20/12 ,  G11B20/18 ,  H03M13/29

CPC分类号： G11B20/10009 ,  G11B20/10055 ,  G11B20/18 ,  G11B20/1809 ,  H03M13/27 ,  H03M13/2957 ,  H03M13/3916 ,  H03M13/3927

摘要： A small circuit-size data recording/reproduction device using repeated decoding for realizing high-speed data reproduction from a recording medium containing data recorded with a high density. In order to achieve this object, the data recording/reproducing device using repeated decoding records a data block in which input data is encoded by a convolution symbol on a recording medium, reproduces it via a partial response channel, and decodes the data block from the reproduction signal by using repeated decoding using likelihood information. The device includes means for dividing the data block encoded by the convolution symbol into a plurality of data sub-blocks and means for recording the data sub-blocks at positions not adjacent to each other on the recording medium.

公开(公告)号：EP2323327A2

公开(公告)日：2011-05-18

申请号：EP10191408.3

申请日：2010-11-16

申请人： NXP B.V.

发明人： Van Houtem, Wilhelmus J. ,  Willems, Frans M.J.

IPC分类号： H04L27/26 ,  H03M3/04

CPC分类号： H04L27/2649 ,  H03M7/3002 ,  H03M13/23 ,  H03M13/2957 ,  H03M13/31 ,  H03M13/3994 ,  H03M13/6325 ,  H04L1/0047 ,  H04L1/005 ,  H04L1/0054 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0071 ,  H04L25/03203 ,  H04L2001/0093 ,  H04L2025/03414

摘要： A system and method for demodulating and decoding a differentially encoded modulation code from a coded orthogonal frequency division multiplexing (COFDM) transmitter involves partitioning the differentially encoded modulation code into two-dimensional code blocks and demodulating and decoding the two-dimensional code blocks to produce demodulated and decoded information.

摘要翻译： 的系统和用于解调的方法和从一个编码的正交频分复用进行解码的差分编码调制码（COFDM）发射机涉及到将所述差分编码调制码转换为二维码块和解调和解码所述二维码块以产生解调 和解码的信息。

公开(公告)号：EP2299598A2

公开(公告)日：2011-03-23

申请号：EP10011906.4

申请日：2001-03-22

申请人： MITSUBISHI DENKI KABUSHIKI KAISHA

发明人： Matsumoto, Wataru

IPC分类号： H03M13/27 ,  H03M13/29

CPC分类号： H03M13/258 ,  H03M13/271 ,  H03M13/2957 ,  H03M13/3988

摘要： A turbo encoder has a configuration provided with rearrangement unit which generates N types of random series by arranging random series generated by using prime numbers in a buffer of N (where N is a natural number) rows x M (where M is a natural number) columns and rearranging bits in rows by using the random series, generating a final rearrangement pattern by mapping interleaver-length data series on the rearranged N types of random series, and replacing rows in the mapped data series in accordance with a predetermined rule, and finally reading the generated rearrangement pattern in columns.

公开(公告)号：EP2297859A1

公开(公告)日：2011-03-23

申请号：EP09762139.5

申请日：2009-06-09

申请人： NXP B.V.

发明人： DILONARDO, Angelo Raffaele ,  ENGIN, Nur

IPC分类号： H03M13/27 ,  H03M13/29

CPC分类号： H03M13/2775 ,  H03M13/2739 ,  H03M13/2753 ,  H03M13/2764 ,  H03M13/2957 ,  H03M13/6519 ,  H03M13/6525 ,  H03M13/6544

摘要： A data processing system, a turbo decoding system, an address generator and a method of reconfiguring a turbo decoding method is provided. The data processing system (101) comprises the turbo decoding system (100). The turbo decoding system (100) comprises electronic circuits. The electronic circuits comprises: a memory (108), the address generator (102), and a Soft Input Soft Output decoder (106). The address generator (102) is operative to produce a sequence of addresses according to an interleaving scheme. The address generator can support multiple interleaving schemes. The address generator (102) is operative to receive reconfiguration information. The address generator (102) is operative to reconfigure during operational use the interleaving scheme in dependency on the reconfiguration information.

公开(公告)号：EP2294698A1

公开(公告)日：2011-03-16

申请号：EP09739505.7

申请日：2009-04-27

申请人： QUALCOMM Incorporated

发明人： SUN, Thomas ,  TIAN, Tao ,  KRISHNAMOORTHI, Raghuraman ,  JIANG, Jing ,  LING, Fuyun

IPC分类号： H03M13/29 ,  H04L1/00

CPC分类号： H03M13/2957 ,  H04L1/0066 ,  H04L1/0071

摘要： A turbo-coded data block is processed for transmission on a wireless communication link by scheduling a plurality of portions of the block for transmission during respectively corresponding transmit intervals that are temporally separated from one another. The block portions are transmitted during the respectively corresponding transmit intervals according to the scheduling.

公开(公告)号：EP2293452A1

公开(公告)日：2011-03-09

申请号：EP10012474.2

申请日：2001-07-03

申请人： LG Electronics Inc.

发明人： Yoon, Young Woo ,  Lee, Young Jo ,  Kim, Gi Jun ,  Kwon, Soon Yil

IPC分类号： H03M13/00 ,  H03M13/23 ,  H03M13/27 ,  H03M13/29

CPC分类号： H04L1/08 ,  H03M13/09 ,  H03M13/23 ,  H03M13/27 ,  H03M13/29 ,  H03M13/2957 ,  H03M13/6356 ,  H03M13/6362 ,  H04L1/0009 ,  H04L1/0013 ,  H04L1/0043 ,  H04L1/0059 ,  H04L1/0066 ,  H04L1/0069 ,  H04L1/0071

摘要： Method of matching the size of a coded data block to the size of an interleaver in a 3GPP2 system comprising a step of turbo encoding a data block with a turbo code of rate 1/n, a step of forming pairs of n-bit bit-groups from the turbo encoded bits, a step of selecting evenly distributed pairs of n-bit bit-groups, and a step of applying a puncturing pattern to the pairs of n-bit bit-groups which prescribes puncturing a bit of a first constituent code of the turbo code in its first n-bit bit-group and puncturing a bit of a second constituent code in its second n-bit bit-group, so that a regular puncturing distance is obtained for both constituent codes.

摘要翻译： 将编码数据块的大小与3GPP2系统中的交织器的大小进行匹配的方法，包括以速率为1 / n的turbo码对数据块进行turbo编码的步骤，形成n位位 - 来自turbo编码比特的组，选择均匀分布的n比特比特组对的步骤，以及将打孔模式应用于规定打破第一组成码的比特的n比特比特组对的步骤 在其第一n位比特组中对turbo码进行删截，并在其第二n位比特组中打孔第二组成码的比特，从而获得两个组成码的规则穿孔距离。

公开(公告)号：EP2267903A2

公开(公告)日：2010-12-29

申请号：EP10009796.3

申请日：1999-12-03

申请人： Qualcomm Incorporated

发明人： Rowitch, Douglas, N. ,  Ling, Funyun

IPC分类号： H03M13/27

CPC分类号： H03M13/2789 ,  H03M13/271 ,  H03M13/275 ,  H03M13/2764 ,  H03M13/2771 ,  H03M13/2957

摘要： A turbo code interleaver (100) using linear congruential sequences may be employed as a two-dimensional interleaver (16) in a turbo coder (10) that also includes first and second constituent encoders (12, 14). The interleaver (16) and the first encoder (12) are each configured to receive input bits. The first encoder (12) produces output symbols (22, 24) therefrom. The interleaver (16) receives the input bits (20) sequentially by row. A linear congruential sequence recursion algorithm within the interleaver (16) serves to pseudo-randomly rearrange, or shuffle, the bits within each row of the interleaver (16). The bits (26) are then output from the interleaver sequentially by column. The second encoder (14) is configured to receive the interleaved bits from the interleaver. The second encoder (14) produces output symbols (28) therefrom.; The two streams of output symbols (22, 24) are multiplexed together, with appropriate puncturing. If desired, the linear congruential recursion sequence can be generated in reverse. Also if desired, a bit reversal technique can be used in the interleaver (16) to rearrange, or shuffle, the rows of the interleaver (16).

摘要翻译： 在包括第一和第二组成编码器（12,14）的turbo编码器（10）中，可以采用使用线性同余序列的turbo码交织器（100）作为二维交织器（16）。 交织器（16）和第一编码器（12）都被配置为接收输入比特。 第一编码器（12）从其产生输出符号（22,24）。 交织器（16）逐行地接收输入比特（20）。 交织器（16）内的线性同余序列递归算法用于对交织器（16）的每行内的比特进行伪随机重排或混洗。 然后从列中逐行地从交织器输出比特（26）。 第二编码器（14）被配置为从交织器接收交织的比特。 第二编码器（14）从其产生输出符号（28）。 输出符号（22,24）的两个流被多路复用在一起，并进行适当的删截。 如果需要，可以相反地生成线性同余递归序列。 此外，如果需要，可以在交织器（16）中使用位反转技术来重排或混洗交织器（16）的行。

公开(公告)号：EP2242182A3

公开(公告)日：2010-12-29

申请号：EP10166532.1

申请日：2003-12-03

申请人： InterDigital Technology Corporation

发明人： Pietraski, Philip J. ,  Sternberg, Gregory S.

IPC分类号： H03M13/35 ,  H03M13/27

CPC分类号： H03M13/2771 ,  H03M13/005 ,  H03M13/2792 ,  H03M13/2957 ,  H03M13/6362 ,  H03M13/6381 ,  H04L1/0067

摘要： Detecting, avoiding and/or correcting problematic puncturing patterns in parity bit streams used when implementing punctured Turbo codes is achieved without having to avoid desirable code rates. This enables identification/avoidance of regions of relatively poor Turbo code performance. Forward error correction comprising Turbo coding and puncturing achieves a smooth functional relationship between any measure of performance and the effective coding rate resulting from combining the lower rate code generated by the Turbo encoder (600) with puncturing of the parity bits. In one embodiment, methods to correct/avoid degradations due to Turbo coding are implemented by puncturing interactions when two or more stages of rate matching (610, 620) are employed.

摘要翻译： 当实现收缩Turbo码时，检测，避免和/或校正奇偶比特流中的有问题的删余模式，而不必避免期望的码率。 这使得能够识别/避免Turbo代码性能相对较差的区域。 包括Turbo编码和打孔的前向纠错实现了任何性能测量和由Turbo编码器（600）生成的较低码率码与奇偶校验位的打孔组合所得到的有效码率之间的平滑函数关系。 在一个实施例中，当采用两级或更多级速率匹配（610,620）时，通过对相互作用进行收缩来实现纠正/避免由Turbo编码引起的退化的方法。