公开(公告)号：EP4392976A1

公开(公告)日：2024-07-03

申请号：EP22862191.8

申请日：2022-07-15

申请人： NEO Semiconductor, Inc.

发明人： HSU, Fu-Chang

IPC分类号： G11C16/12 ,  G11C16/24

CPC分类号： G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/00220130101 ,  G11C2207/228120130101 ,  G11C7/08 ,  G11C7/065 ,  G11C7/12 ,  G11C7/18

公开(公告)号：EP4210060B1

公开(公告)日：2024-07-03

申请号：EP22152221.2

申请日：2022-01-19

IPC分类号： G11C7/12 ,  G11C7/10 ,  G11C7/18 ,  G11C5/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26

CPC分类号： G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/10 ,  G11C7/18 ,  G11C7/12 ,  G11C5/066 ,  G11C7/1084 ,  Y02D10/00

公开(公告)号：EP3918601B1

公开(公告)日：2024-07-03

申请号：EP19772938.7

申请日：2019-09-05

IPC分类号： G06F12/02 ,  G06N3/08 ,  G11C7/10 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C27/00 ,  G06N3/044 ,  G06N3/063 ,  G06N3/045 ,  G06N3/048 ,  G06N3/065 ,  G06N3/04 ,  G11C11/54 ,  G11C16/12 ,  G11C16/24 ,  G11C16/16 ,  G11C16/30 ,  G11C16/14

CPC分类号： G11C11/54 ,  G11C16/3459 ,  G11C27/005 ,  G06N3/08 ,  G11C16/24 ,  G11C7/1006 ,  G11C16/10 ,  G11C16/0425 ,  G11C16/0433 ,  G06F12/0246 ,  G06F2212/720120130101 ,  G06F2212/720220130101 ,  G06N3/065 ,  G06N3/048 ,  G06N3/044 ,  G06N3/045

公开(公告)号：EP4390936A1

公开(公告)日：2024-06-26

申请号：EP23219178.3

申请日：2023-12-21

申请人： Commissariat à l'Energie Atomique et aux Energies Alternatives

发明人： SABBIONE, Chiara ,  NAVARRO, Gabriele ,  TESSAIRE, Magali ,  FREI, Michel Ranjit ,  NISTOR, Lavinia-Elena

IPC分类号： G11C13/00 ,  H10N70/20

CPC分类号： H10N70/8828 ,  H10N70/231 ,  H10N70/041 ,  H10N70/826 ,  G11C13/0004 ,  H10N70/026 ,  H10N70/235

摘要： The invention relates to a material stack, a microelectronic device that integrates such stack and a method for obtaining such stack.
A non-limitative application of the invention relates to Phase-Change Memory device.
The material stack 10 for microelectronic device 1 comprises:
a. A substrate 11,
b. A first undoped crystalline layer 12 on the substrate, said undoped crystalline layer having a thickness superior to 4 nm, and
c. A Si-doped crystalline chalcogenide layer 13 on the undoped crystalline layer, said Si-doped crystalline chalcogenide layer being doped with less than 20 at.%, and preferably less than 12 at.%, of Si.
The provided material stack shows a satisfying stability contributing to retard the stack possible reorganization (i.e. intermixing) that could happen during the manufacturing of the material stack and during the subsequent manufacturing of said microelectronic device.

公开(公告)号：EP4390933A1

公开(公告)日：2024-06-26

申请号：EP22315346.1

申请日：2022-12-21

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： Sabbione, Chiara ,  Navarro, Gabriele ,  Tessaire, Magali ,  Frei, Michel Ranjit ,  Nistor, Lavinia-Elena

IPC分类号： G11C13/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： H10N70/8828 ,  H10N70/231 ,  H10N70/041 ,  H10N70/826 ,  G11C13/0004 ,  H10N70/026 ,  H10N70/235

摘要： The invention relates to a material stack, a microelectronic device that integrates such stack and a method for obtaining such stack.
A non-limitative application of the invention relates to Phase-Change Memory device. The material stack (10) for microelectronic device (1) comprises:
a. A substrate (11),
b. A first undoped crystalline layer (12) on the substrate, said undoped crystalline layer having a thickness superior to 4 nm, and
c. A Si-doped crystalline chalcogenide layer (13) on the undoped crystalline layer, said Si-doped crystalline chalcogenide layer being doped with less than 20 at.%, and preferably less than 12 at.%, of Si.
The provided material stack shows a satisfying stability contributing to retard the stack possible reorganization (i.e. intermixing) that could happen during the manufacturing of the material stack and during the subsequent manufacturing of said microelectronic device.

公开(公告)号：EP4390927A1

公开(公告)日：2024-06-26

申请号：EP23199473.2

申请日：2023-09-25

申请人： Samsung Electronics Co., Ltd.

发明人： JUNG, Kwansuk ,  KO, Sungwon ,  CHANG, Hoyoung ,  CHO, Youngjin

IPC分类号： G11C7/10 ,  G11C16/26 ,  G11C16/32

CPC分类号： G11C16/26 ,  G11C16/32 ,  G11C7/1042

摘要： An operation method of a memory controller (110) includes sequentially transmitting a first read command for the first plane (PLNa) and a second read command for the second plane (PLNb) to the nonvolatile memory device (120), transmitting a first status read command corresponding to the first read command to the nonvolatile memory device (120), transmitting a first memory access command corresponding to the first read command to the nonvolatile memory device (120) based on first status information, receiving first read data that is output from the nonvolatile memory device (120), skipping issuing of a status read command corresponding to the second read command and transmitting a second memory access command corresponding to the second read command to the nonvolatile memory device (120), after receiving the first read data, and receiving second read data that is output from the nonvolatile memory device (120).

公开(公告)号：EP4390781A1

公开(公告)日：2024-06-26

申请号：EP23218412.7

申请日：2023-12-20

申请人： Commissariat à l'énergie atomique et aux énergies alternatives

发明人： JADOT, Baptiste ,  BILLIOT, Gérard ,  THONNART, Yvain

IPC分类号： G06N10/40 ,  H03M1/66 ,  G11C27/02 ,  H01L29/423

CPC分类号： G06N10/40 ,  G11C27/024 ,  H01L29/423 ,  G06N10/00 ,  G06N3/065

摘要： Ce circuit (100), relié au circuit quantique par des lignes de polarisation (11, 12, 13, 14), comporte : un convertisseur numérique analogique - DAC (102) délivrant une tension analogique (Ve) ; des cellules mémoires (110, 120, 130, 140), connectées en parallèle en sortie du DAC, chaque cellule mémoire comportant un interrupteur (I1, I2, I3, I4) et une capacité (C1, C2, C3, C4), la capacité mémorisant un niveau de potentiel auquel maintenir une ligne de polarisation connectée en sortie de la cellule mémoire ; et, un moyen de génération de signaux de commande (104) générant, en synchronisation avec le DAC, un signal de commande pour chaque interrupteur de chaque cellule mémoire, le signal de commande, une valeur de la capacité d'une cellule mémoire étant sélectionnée pour rendre négligeable une capacité parasite affectant la ligne de polarisation reliée à ladite cellule mémoire et qui circule parallèlement à une ligne de polarisation voisine.

公开(公告)号：EP3924967B1

公开(公告)日：2024-06-26

申请号：EP20913067.3

申请日：2020-04-17

IPC分类号： G11C8/08 ,  G11C16/08 ,  H10B41/50 ,  H10B43/50

CPC分类号： G11C8/08 ,  H10B12/50 ,  H10B41/40 ,  H10B41/50 ,  H10B43/50 ,  H10B43/40

公开(公告)号：EP4386756A1

公开(公告)日：2024-06-19

申请号：EP23215662.0

申请日：2023-12-11

申请人： Samsung Electronics Co., Ltd.

发明人： CHOI, Yonghyuk ,  YU, Jaeduk ,  LEE, Yohan

IPC分类号： G11C16/34 ,  G11C16/04 ,  G11C29/52 ,  G11C29/44 ,  G11C5/06 ,  G11C11/56 ,  G11C13/00 ,  G11C16/26 ,  G11C16/32 ,  G11C29/12 ,  G11C29/02

CPC分类号： G11C16/3404 ,  G11C16/32 ,  G11C16/26 ,  G11C29/52 ,  G11C2029/120220130101 ,  G11C5/063 ,  G11C11/5642 ,  G11C16/0483 ,  G11C13/0033 ,  G11C29/025 ,  G11C29/4401

摘要： A memory device includes a word line area that is between a bit line and a common source line. The word line area includes a plurality of stacks. A first area includes first stacks with a first resistance value in the word line area, a second area includes second stacks with a second resistance value in the word line area, wherein the second resistance value is different from the first resistance value, a third area includes third stacks with a third resistance value that different from the first resistance value, and a processor is configured to control a recovery sequence of the first area, the second area, and the third area.

公开(公告)号：EP4386753A1

公开(公告)日：2024-06-19

申请号：EP21961713.1

申请日：2021-10-26

申请人： Huawei Technologies Co., Ltd.

发明人： CAI, Jiangzheng ,  CHENG, Kuan ,  BU, Mingen ,  ZHANG, Yuqing

IPC分类号： G11C5/14

CPC分类号： G11C5/14

摘要： This application provides a single-ended memory, and relates to the field of storage technologies, to resolve a problem of a low read speed of a conventional single-ended memory. The single-ended memory includes a storage unit distributed in an array, where the storage unit is connected to a read bit line and a read word line, the read bit line is connected to a precharge unit through a column selection unit, the read bit line is connected to an output end of a leakage current compensation unit through the column selection unit, the read bit line is further connected to a control end of the leakage current compensation unit through a feedback circuit, and when determining that a level of the read bit line is lower than a first predetermined value, the feedback circuit outputs a feedback signal to the control end of the leakage current compensation unit, to stop the leakage current compensation unit from charging the read bit line through the output end.