公开(公告)号：EP0877382A3

公开(公告)日：1999-07-07

申请号：EP98201557.0

申请日：1992-04-16

申请人： MITSUBISHI DENKI KABUSHIKI KAISHA ,  MITSUBISHI ELECTRIC ENGINEERING CO., LTD.

发明人： Dosaka, Katsumi, c/o Mitsushiki Denki K.K. LSI ,  Kumanoya, Masaki, c/o Mitsushiki Denki K.K. LSI ,  Yamazaki, Akira, c/O Mitsubishi Denki K.K. LSI ,  Iwamoto, Hisashi, c/o Mitsubishi Denki K.K. LSI ,  Konishi, Yasuhiro, c/o Mitsubishi Denki K.K. LSI ,  Hayano, Kouji, c/o Mitsubishi Denki K.K. ,  Abe, Hideaki, c/o Mitsubishi Denki K.K. ,  Himukashi, Katsumitsu, c/o Mitsubishi E. E. Co.Ltd ,  Ishizuka, Yasuhiro, c/o Mitsubishi E. E. Co.Ltd ,  Saiki, Tsukasa, c/o Mitsubishi E. E. Co.Ltd

IPC分类号： G11C11/00 ,  G11C11/418 ,  G11C11/419

CPC分类号： G11C8/00 ,  G06F12/0893 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02D10/13

摘要： A semiconductor memory device includes a DRAM (100), an SRAM (200) and a bi-direction transfer gate circuit (210) provided between SRAM (200) and DRAM (100). SRAM array (201; 560) includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer (255). The semiconductor memory device further includes an additional function control circuit (229) for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths (GIL) and (LIL) and data reading paths (LOL) and (GOL) are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：EP0877381A2

公开(公告)日：1998-11-11

申请号：EP98201556.2

申请日：1992-04-16

申请人： MITSUBISHI DENKI KABUSHIKI KAISHA ,  MITSUBISHI ELECTRIC ENGINEERING CO., LTD.

发明人： Dosaka, Katsumi, c/o Mitsubishi Denki K.K. LSI ,  Kumanoya, Masaki, c/o Mitsubishi Denki K.K. LSI ,  Yamazaki, Akira, c/o Mitsubishi Denki K.K. LSI ,  Iwamoto, Hisashi, c/o Mitsubishi Denki K.K. LSI ,  Konishi, Yasuhiro, c/o Mitsubishi Denki K.K. LSI ,  Hayano, Kouji, Mitsubishi Denki KK. Kitaitami Sei. ,  Abe, Hideaki, Mitsubishi Denki KK. Kitaitami Sei. ,  Himukashi, Katsumitsu, Mitsubishi Elec.Eng.Co.Ltd. ,  Ishizuka, Yasuhiro, Mitsubishi Elec.Eng.Co.Ltd. ,  Saiki, Tsukasa, Mitsubishi Elec. Eng. Co. Ltd.

IPC分类号： G11C11/00 ,  G11C11/418 ,  G11C11/419

CPC分类号： G11C8/00 ,  G06F12/0893 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02D10/13

摘要： A semiconductor memory device includes a DRAM (100), an SRAM (200) and a bi-direction transfer gate circuit (210) provided between SRAM (200) and DRAM (100). SRAM array (201; 560) includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer (255). The semiconductor memory device further includes an additional function control circuit (229) for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths (GIL) and (LIL) and data reading paths (LOL) and (GOL) are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：EP0426597B1

公开(公告)日：1995-11-08

申请号：EP90480144.6

申请日：1990-09-21

申请人： International Business Machines Corporation

发明人： Chan, Yuen Hung

IPC分类号： G11C8/00 ,  G11C11/418 ,  G11C7/00

CPC分类号： G11C8/12 ,  G11C8/10 ,  G11C11/418

公开(公告)号：EP0356983B1

公开(公告)日：1995-11-02

申请号：EP89115897.4

申请日：1989-08-29

申请人： NEC CORPORATION

发明人： Ando, Manabu

IPC分类号： G11C7/00 ,  G11C8/00 ,  G11C11/418 ,  G11C11/419

CPC分类号： G11C7/22 ,  G11C7/12 ,  G11C8/18 ,  G11C11/418 ,  G11C11/419

公开(公告)号：EP0660330A2

公开(公告)日：1995-06-28

申请号：EP94118906.0

申请日：1994-12-01

申请人： MOTOROLA, INC.

发明人： Sparks, Robert Wayne ,  Harwood, Wallace Baker, III ,  Jew, Thomas ,  Eifert, James Bradley

IPC分类号： G11C8/00 ,  G11C11/418

CPC分类号： G11C8/00 ,  G11C11/418

摘要： An SRAM (18) having a low power operating mode is provided for a data processing system (10). A programmable control bit is used for switching the SRAM (18) from a one clock cycle operating mode to a two clock cycle, or low power, operating mode. Initially, during the two cycle operating mode, only a bus interface unit (41) is active. During the first cycle, an address is compared to determine if the address is a valid address. If the address is valid, address decoders (42) are enabled, and a data transfer is completed on the second clock cycle. If the address is not valid, the address decoders (42) remain disabled and memory array (43) remains in a quiescent state consuming minimum power. During one cycle mode, the SRAM (18) decodes every address in order to respond in one clock cycle to a valid address.

摘要翻译： 为数据处理系统（10）提供具有低功率工作模式的SRAM（18）。 可编程控制位用于将SRAM（18）从一个时钟周期工作模式切换到两个时钟周期或低功耗工作模式。 最初，在两个循环操作模式期间，只有总线接口单元（41）是激活的。 在第一个周期中，比较地址以确定地址是否为有效地址。 如果地址有效，则地址解码器（42）被使能，并且数据传输在第二时钟周期完成。 如果地址无效，则地址解码器（42）保持禁用，并且存储器阵列（43）保持处于消耗最小功率的静止状态。 在一个周期模式中，SRAM（18）解码每个地址，以便在一个时钟周期内响应一个有效地址。

公开(公告)号：EP0360526B1

公开(公告)日：1994-11-23

申请号：EP89309444.1

申请日：1989-09-18

申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

发明人： Goto, Shigeki ,  Kato, Yoshiharu

IPC分类号： G11C7/00 ,  G11C11/418 ,  G11C8/04

CPC分类号： G11C7/1087 ,  G11C7/1078 ,  G11C7/20 ,  G11C8/04 ,  G11C11/418

公开(公告)号：EP0437402A3

公开(公告)日：1992-10-21

申请号：EP91400043.5

申请日：1991-01-10

申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

发明人： Yamaguchi, Shuhei

IPC分类号： H03K3/356 ,  G11C11/418 ,  G11C11/419 ,  G11C11/412

CPC分类号： H03K3/356017

摘要： A level changing semiconductor integrated circuit comprises two current paths in which emitters of first and second bipolar transistors (13, 14) are each connected in series to one terminal of first and second MOSFETs (15, 16), respectively. The current paths are disposed between a high-potential power source (Vcc) and a low-potential power source (Vss). Gates of the first and second MOSFETs are cross-connected to the emitters of the bipolar transistors of opposite current paths. The emitters of the first and second bipolar transistors provide output signals. At least two kinds of input signals (IN1, IN2) having different signal levels are simultaneously applied to respective input units of the current paths.

摘要翻译： 电平改变半导体集成电路包括两个电流路径，其中第一和第二双极晶体管（13,14）的发射极分别串联连接到第一和第二MOSFET（15,16）的一个端子。 电流路径设置在高电位电源（Vcc）和低电位电源（Vss）之间。 第一和第二MOSFET的栅极交叉连接到相反电流路径的双极晶体管的发射极。 第一和第二双极晶体管的发射极提供输出信号。 具有不同信号电平的至少两种输入信号（IN1，IN2）被同时施加到电流路径的各个输入单元。

公开(公告)号：EP0439154A3

公开(公告)日：1992-08-19

申请号：EP91100848.0

申请日：1991-01-23

申请人： SEIKO EPSON CORPORATION

发明人： Kayamoto, Hiroshi, c/o Seiko Epson Corporation ,  Nakajima, Masahiko, c/o Seiko Epson Corporation

IPC分类号： G11C8/00 ,  G11C5/14 ,  G11C11/415 ,  G11C11/419 ,  G11C11/418

CPC分类号： G11C11/419 ,  G11C5/145 ,  G11C8/08 ,  G11C11/415 ,  G11C11/418

摘要： In the peripheral circuit of a static RAM comprised by memory cells (1) of the polysilicon high resistance type, is provided a word line voltage transformation circuit (50) which sets the potential of a selected word line (WL) during writing operation to be the potential V VOL , the value of which is higher than that of the supplied potential V DD . The word line voltage transformation circuit comprises a ring-oscillator circuit, a transformation timing signal generating circuit, a step-up gate control signal generating circuit, a stepped-up potential generating circuit, a word line supplied potential mixing circuit, and a word line potential supply control circuit.

公开(公告)号：EP0393434A3

公开(公告)日：1992-07-08

申请号：EP90106587.0

申请日：1990-04-06

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： Mattausch, Hans-Jürgen, Dr. rer. nat. ,  Hoppe, Bernhard, Dr. rer. nat. (bei Dr.W. Krüger) ,  Neuendorf, Gerd, Dipl.-Ing. ,  Schmitt-Landsiedel, Doris, Dr. rer. nat. ,  Pfleiderer, Hans-Jörg, Prof. Dr.-Ing. ,  Wurm, Maria

IPC分类号： G11C5/02 ,  G11C8/00 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419

CPC分类号： G11C11/419 ,  G11C5/025 ,  G11C8/12 ,  G11C11/417 ,  G11C11/418

摘要： Die Erfindung betrifft einen statischen Speicher mit mehreren Hierarchieebenen (H0...H3). Hierfür werden günstige Realisierungsmöglichkeiten angegeben, da der Flächenaufwand für die Ansteuer- und Ausleseschaltungen in der zweiten Hierarchieebene (H1) besonders kritisch sind. Vorteilhaft werden hierbei Speicherzellen eingesetzt, die ein starkes Zellsignal liefern, so daß ein geringer Aufwand in der Leseschaltung nötig ist. Durch Verlagerung von Peripherieschaltungen in höherer Hierarchieebenen ergibt sich eine verringerte Zugriffszeit und ein verringerter Flächenbedarf.

公开(公告)号：EP0439154A2

公开(公告)日：1991-07-31

申请号：EP91100848.0

申请日：1991-01-23

申请人： SEIKO EPSON CORPORATION

发明人： Kayamoto, Hiroshi, c/o Seiko Epson Corporation ,  Nakajima, Masahiko, c/o Seiko Epson Corporation

IPC分类号： G11C8/00 ,  G11C5/14 ,  G11C11/415 ,  G11C11/419 ,  G11C11/418

CPC分类号： G11C11/419 ,  G11C5/145 ,  G11C8/08 ,  G11C11/415 ,  G11C11/418

摘要： In the peripheral circuit of a static RAM comprised by memory cells (1) of the polysilicon high resistance type, is provided a word line voltage transformation circuit (50) which sets the potential of a selected word line (WL) during writing operation to be the potential V VOL , the value of which is higher than that of the supplied potential V DD . The word line voltage transformation circuit comprises a ring-oscillator circuit, a transformation timing signal generating circuit, a step-up gate control signal generating circuit, a stepped-up potential generating circuit, a word line supplied potential mixing circuit, and a word line potential supply control circuit.

摘要翻译： 在由多晶硅高电阻型的存储单元（1）构成的静态RAM的外围电路中，提供了一个字线电压变换电路（50），其将写入操作期间所选字线（WL）的电位设置为 电位VVOL，其值高于所提供的电位VDD的电压。 字线电压变换电路包括环形振荡器电路，变换定时信号发生电路，升压门控制信号产生电路，升压电位发生电路，字线供给电位混合电路和字线 电源控制电路。