公开(公告)号：EP1451877A4

公开(公告)日：2009-06-03

申请号：EP02786713

申请日：2002-11-13

申请人： GEN SEMICONDUCTOR INC

发明人： HSHIEH FWU-IUAN ,  SO KOON CHONG

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L29/42368 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/511 ,  H01L29/513 ,  H01L29/7813

摘要： A trench MOSFET device comprising: (a) a silicon substrate of a first conductivity type (preferably N-type conductivity); (b) a silicon epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a body region of a second conductivity type (preferably P-type conductivity) within an upper portion of the epitaxial layer; (d) a trench having trench sidewalls and a trench bottom, which extends into the epitaxial layer from an upper surface of the epitaxial layer and through the body region of the device; (f) an oxide region lining the trench, which comprises a lower segment covering at least the trench bottom and upper segments covering at least upper regions of the trench sidewalls; (g) a conductive region within the trench adjacent the oxide region; and (h) a source region of the first conductivity type within an upper portion of the body region and adjacent the trench. The lower segment of the oxide region is thicker than the upper segments of the oxide region in this embodiment.

公开(公告)号：EP1476894A4

公开(公告)日：2009-02-18

申请号：EP02794456

申请日：2002-12-30

申请人： GEN SEMICONDUCTOR INC

发明人： BLANCHARD RICHARD A

IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L21/22 ,  H01L21/225 ,  H01L21/329 ,  H01L29/06 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L21/2257 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395

摘要： A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first or second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A first layer of polysilicon having a second dopant of the second conductivity type is deposited in the trench. The second dopant is diffused to form a doped epitaxial region adjacent to the trench and in the epitaxial layer. A second layer of polysilicon having a first dopant of the first conductivity type is subsequently deposited in the trench. The first and second dopants respectively located in the second and first layers of polysilicon are interdiffused to achieve electrical compensation in the first and second layers of polysilicon. Finally, at least one region of the second conductivity type is formed over the voltage sustaining region to define a junction therebetween.

公开(公告)号：EP1454361A4

公开(公告)日：2009-01-21

申请号：EP02803696

申请日：2002-11-20

申请人： GEN SEMICONDUCTOR INC

发明人： HSHIEH FWU-LUAN ,  SO KOON CHONG ,  AMATO JOHN E ,  TSUI YAN MAN

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/45

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/456

摘要： A trench MOSFET transistor device and a method of making the same. The device comprises: (a) a silicon substrate of first conductivity type; (b) a silicon epitaxial layer of first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type provided within an upper portion of the body region and adjacent the trench; (h) an upper region of second conductivity type within an upper portion of the body region and adjacent the source region, the upper region having a higher majority carrier concentration than the body region; and (i) a source contact region disposed on the epitaxial layer upper surface, wherein the source contact region comprises a doped polycrystalline silicon contact region in electrical contact with the source region as well as an adjacent metal contact region in electrical contact with the source region and with the upper region.

公开(公告)号：EP1454360A4

公开(公告)日：2008-12-17

申请号：EP02782334

申请日：2002-11-20

申请人： GEN SEMICONDUCTOR INC

发明人： HSHIEH FWU-IUAN ,  SO KOON CHONG ,  AMATO JOHN E ,  TSUI YAN MAN

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/08 ,  H01L29/36

CPC分类号： H01L29/0878 ,  H01L29/7813

摘要： A method of forming a trench MOSFET device includes depositing an epitaxial layer over a substrate, both having the first conductivity type, the epitaxial layer having a lower majority carrier concentration than the substrate, forming a body region of a second conductivity type within an upper portion of the epitaxial layer, etching a trench extending into the epitaxial layer from an upper surface of the epitaxial layer, the trench extending to a greater depth from the upper surface of the epitaxial layer than the body region, forming a doped region of the first conductivity type between a bottom portion of the trench and substrate, the doped region having a majority carrier concentration that is lower than that of the substrate and higher than that of the epitaxial layer, wherein the doped region is diffused and spans 100% of the distance from the trench bottom portion to the substrate, forming an insulating layer lining at least a portion of the trench, forming a conductive region within the trench adjacent the insulating layer and forming a source region of said first conductivity type within an upper portion of the body region and adjacent the trench.

公开(公告)号：EP1446839A4

公开(公告)日：2008-12-10

申请号：EP02789331

申请日：2002-10-30

申请人： GEN SEMICONDUCTOR INC

发明人： HSHIEH FWU-LUAN ,  SO KOON CHONG ,  NELSON WILLIAM JOHN ,  AMATO JOHN E

IPC分类号： H01L21/8234 ,  H01L29/78 ,  H01L21/336 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417

CPC分类号： H01L29/7813 ,  H01L29/0653 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/7809 ,  H01L29/7811

摘要： A trench DMOS transistor device that comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of a second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type within an upper portion of the body region and adjacent the trench; and (h) one or more low resistivity deep regions extending into the device from an upper surface of the epitaxial layer. The low resistivity deep region acts to provide electrical contact with the substrate, which is a common drain region for the device. By constructing a trench DMOS transistor device in this fashion, source, drain and gate contacts can all be provided on a single surface of the device.

公开(公告)号：EP1550150A4

公开(公告)日：2009-08-19

申请号：EP03751848

申请日：2003-08-11

申请人： GEN SEMICONDUCTOR INC

发明人： BLANCHARD RICHARD A

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  G11C16/04

CPC分类号： H01L29/7813 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7802 ,  H01L29/7883

摘要： A DMOS device is provided which is equipped with a floating gate having a first and second electrode in close proximity thereto. The floating gate is separated from one of the first and second electrodes by a thin layer of dielectric material whose dimensions and composition permit charge carriers to tunnel through the dielectric layer either to or from the floating gate. This tunneling phenomenon can be used to create a threshold voltage that may be adjusted to provide a precise current by placing a voltage between a programming electrode and the body/source and gate electrode of the device.

公开(公告)号：EP1468439A4

公开(公告)日：2009-01-07

申请号：EP02792552

申请日：2002-12-30

申请人： GEN SEMICONDUCTOR INC

发明人： BLANCHARD RICHARD A

IPC分类号： H01L21/329 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/7802

摘要： A method for fabricating a high voltage power MOSFFT having a voltage sustaining region that includes doped columns formed by rapid diffusion. A high voltage semiconductor device having a substrate of a first or second conductivity type, an epitaxial layer of the first conductivity on the substrate, and a voltage sustaining region formed in the epitaxial layer, the voltage sustaining region including a column having a second conductivity type formed along at least outer sidewalls of a filled trench, the column including at least one first diffused region and a second diffused region, the first diffused region being connected by the second region and the second region having a junction depth measured from the trench sidewall that is less than the junction depth of the first region and a third region of a second conductivity type that extends from the surface of the epitaxial layer to intersect at least one of the first and second regions of second conductivity type.

公开(公告)号：EP1382071A4

公开(公告)日：2009-01-07

申请号：EP02725313

申请日：2002-03-21

申请人： GEN SEMICONDUCTOR INC

发明人： BLANCHARD RICHARD A

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0878

摘要： A double diffused field effect transistor and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type. Next, at least one dopant species, also of the first conductivity type, is introduced into a surface of the substrate so that the substrate has a nonuniform doping profile. An epitaxial layer of the first conductivity type is formed over the substrate and one or more body regions of a second conductivity type are formed within the epitaxial layer. A plurality of source regions of the first conductivity type are then formed within the body regions. Finally, a gate region is formed, which is adjacent to the body regions.

公开(公告)号：EP1454352A4

公开(公告)日：2008-12-31

申请号：EP02792284

申请日：2002-11-20

申请人： GEN SEMICONDUCTOR INC

发明人： HSHIEH FWU-IUAN ,  SO KOON CHONG ,  AMATO JOHN E ,  PRATT BRIAN D

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L21/823487 ,  H01L29/1095 ,  H01L29/7813 ,  Y10S148/126

摘要： A method is provided for forming shallow and deep dopant implants adjacent source regions of a first conductivity type within an upper portion of an epitaxial layer in a trench MOSFET device. The method comprises: (a) forming a patterned implantation mask over the epitaxial layer, wherein the patterned implantation mask comprises a patterned insulating region and covers at least a portion of the source regions, and wherein the patterned implantation mask has apertures over at least portions of the epitaxial layer adjacent the source regions; (b) forming shallow dopant regions by a process comprising: (1) implanting a first dopant of a second conductivity type at a first energy level within an upper portion of the epitaxial layer through the apertures and (2) diffusing the first dopant at elevated temperatures to a first depth from an upper surface of the epitaxial layer; (c) forming deep dopant regions by a process comprising: (1) implanting a second dopant of the second conductivity type at a second energy level within an upper portion of the epitaxial layer through the apertures and (2) diffusing the second dopant at elevated temperatures to a second depth from the upper surface of the epitaxial layer; and (d) enlarging apertures in the patterned insulating region. In this method, the second energy level is greater than the first energy level, the second depth is greater than the first depth, and the first and second dopants can be the same or different. The method of the present invention can be used, for example, to form a device that comprises a plurality of trench MOSFET cells.

公开(公告)号：EP1425791A4

公开(公告)日：2006-02-15

申请号：EP02766116

申请日：2002-08-23

申请人： GEN SEMICONDUCTOR INC

发明人： BLANCHARD RICHARD A ,  HSHIEH FWU-IUAN ,  SO KOON CHONG

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/06 ,  H01L29/06 ,  H01L29/41 ,  H01L29/47 ,  H01L29/78 ,  H01L29/872

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/7806 ,  H01L29/7813

摘要： A merged device is that comprises a plurality of MOSFET cells and a plurality of Schottky rectifier cells, as well as a method of designing and making the same. According to an embodiment of the invention, the MOSFET cells comprise: (a) a source region of first conductivity type formed within an upper portion of a semiconductor region, (b) a body region of second conductivity type formed within a middle portion of the semiconductor region, (c) a drain region of first conductivity type formed within a lower portion of the semiconductor region, and (d) a gate region provided adjacent the source region, the body region, and the drain region. The Schottky diode cells in this embodiment are disposed within a trench network and comprise a conductor portion in Schottky rectifying contact with the lower portion of the semiconductor region. At least one MOSFET cell gate region is positioned along a sidewall of the trench network and adjacent at least one Schottky diode cell in this embodiment.