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1.发明公开Electronic module comprising a layer containing integrated circuit die and a method for making the same 审中-公开具有包含集成电路及其制造一个层的电子器件
公开(公告)号：EP1724835A1
公开(公告)日：2006-11-22
申请号：EP05104103.6
申请日：2005-05-17
发明人： Gann, Keith , Boyd, W. Eric
IPC分类号： H01L25/10 , H01L23/538 , H01L21/48
CPC分类号： H01L23/5382 , H01L21/485 , H01L24/48 , H01L24/97 , H01L25/105 , H01L2224/32245 , H01L2224/48091 , H01L2224/4826 , H01L2224/48465 , H01L2225/1029 , H01L2225/1064 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A three dimensional electronic module is disclosed. Conventional TSOP packages are modified to expose internal lead frame interconnects, thinned and stacked on a reroute substrate. The reroute substrate comprises conductive circuitry for the input and output of electrical signals from one or more TSOPs in the stack to a ball grid array pattern. The exposed internal lead frames are interconnected and routed on one or more side buses on the module to the reroute substrate for connection to external electronic circuitry. Alternatively, internal wire bonds or ball bonds may be exposed in the TSOP packages and routed to the side bus for interconnection to create a BGA scale module. One or more neolayers may also be bonded to a reroute substrate to create a BGA scale module.
摘要翻译： 一种三维电子模块是游离缺失盘。 常规TSOP封装被修改，以暴露内部引线框架互连，变薄和堆叠在重新路由的基材。 路线变更基板包括用于输入和从堆叠中的一个或多个TSOP电信号输出到球栅阵列图案的导电电路。 露出的内部引线框架相互连接并路由上的一个或多个侧总线模块到重新路由衬底上，用于连接到外部的电子电路。 可替代地，内部引线键合或球键可以在TSOP封装被暴露并路由到侧总线互连来创建一个BGA级模块。 因此一个或多个neolayers可以结合到一个重新路由衬底以创建一个BGA级模块。
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2.发明公开NEURAL PROCESSING MODULE WITH INPUT ARCHITECTURES THAT MAKE MAXIMAL USE OF A WEIGHTED SYNAPSE ARRAY 审中-公开模块具有输入神经处理架构AN突触矩阵极大EXPLOIT
公开(公告)号：EP1247194A2
公开(公告)日：2002-10-09
申请号：EP99967712.3
申请日：1999-12-30
IPC分类号： G06F15/18
CPC分类号： G06N3/063
摘要： A neural processing module (100) is disclosed which combines a weighted synapse array (200) that performs 'primitive arithmetic' (products and sums) in parallel with a weight change architecture and a data input architecture that collectively maximize the use of the weighted synapse array by providing it with signal permutations (310) as frequently as possible. The neural processing module may be used independently, or in combination with other modules in a planar or stacked arrangement.
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公开(公告)号：EP0596075B1
公开(公告)日：2001-08-22
申请号：EP93911250.4
申请日：1993-05-05
发明人： MIYAKE, Michael, K.
CPC分类号： H01L25/0657 , H01L23/481 , H01L2224/0401 , H01L2224/05 , H01L2224/16145 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551
摘要： An integrated stack of layers (22) incorporating a plurality of IC chip layers (26) has an end layer (30) which is formed of dielectric material (or covered with such material). The outer surface (42) of the end layer (30) provides a substantial area for the spaced location of a multiplicity of lead-out terminals (50), to which exterior circuitry can be readily connected. In the preferred embodiment, each lead-out terminal (50) on the outer surface (42) of the end layer (30) is connected to IC circuitry embedded in the stack by means of conducting material in a hole (48) through the end layer (30), and a conductor (trace) (44) on the inner surface (40) of the end layer (30) which extends from the hole to the edge of the end layer, where it is connected by a T-connect to metallization on the access plane face of the stack (22).
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公开(公告)号：EP0852856A1
公开(公告)日：1998-07-15
申请号：EP95935157.0
申请日：1995-09-27
IPC分类号： H04B10
CPC分类号： H04B10/11
摘要： A wireless infrared pulse-transmitting system for communication with electronic components. The receiver (30) for such a system has a radically reduced current (and power) values, which permit a battery-powered receiver to remain on while awaiting transmitter signals. Use of several mosfet transistors operating in the subthreshold region minimizes power. Bandwidth requirements are met, in spite of the low power operation. In order to eliminate amplifier (40) saturation, with the accompanying problem of recovery time which slows the transmission process, clamping circuitry (46) is used to cause instantaneous shunting of the signals when a predetermined signal level is reached.
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5.发明公开FABRICATING ELECTRONIC CIRCUITRY UNIT CONTAINING STACKED IC LAYERS HAVING LEAD REROUTING 失效制作电子电路单元包括具有远期线路堆叠式芯片单据。
公开(公告)号：EP0593666A1
公开(公告)日：1994-04-27
申请号：EP92916059.0
申请日：1992-06-24
发明人： MINIHAN, Joseph, A.
CPC分类号： H01L25/50 , H01L23/525 , H01L23/528 , H01L25/0657 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06593 , H01L2225/06596 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： L'invention concerne un procédé et un produit appliquant des concepts avancés d'une technique en Z dans le domaine des boîtiers électroniques à haute densité de composants. Pour des tranches de silicium classiques contenant des puces (20), on suit des modes opératoires de modification qui créent des puces CI (38) possédant des conducteurs métalliques de deuxième niveau (30) sur la surface supérieure de la couche de passivation (52) (qui couvre le silicium d'origine (48) et l'aluminium ou autre métallisation (44)). Le métal des conducteurs de deuxième niveau (30) est différent de celui de la métallisation dans les circuits intégrés et permet une meilleure conduction électrique. Les puces modifiées (38) sont séparées des tranches (20) et sont ensuite empilées pour former des dispositifs à circuits intégrés multicouches (60). Une pile comporte un ou plusieurs plans d'accès (64). Après superposition, et avant application de la métallisation sur le plan d'accès, une opération d'attaque chimique enlève tout aluminium (ou autre matériau) qui pourrait interférer avec la métallisation formée sur le plan d'accès. Des plots métalliques (92) sont formés en contact avec les cosses des conducteurs de deuxième niveau (30) sur les puces empilées. Les plots et les cosses sont formés de la même matière métallique afin d'optimiser le rendement de conduction des connexions T.
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公开(公告)号：EP0465591A4
公开(公告)日：1994-03-02
申请号：EP90906503
申请日：1990-03-23
发明人： WALL, LLEWELLYN, E.
CPC分类号： H03M1/123 , H01L25/043 , H01L2924/0002 , H03M1/56 , H03M1/58 , H01L2924/00
摘要： A multi-layer Z-technology module (20) having a two dimensional photodetector (24) mosaic is disclosed, in which the function of A/D signal conversion is accomplished in each on-chip channel. In order to satisfy the power and real estate limitations of the modules, a substantial part of the A/D conversion circuitry is located off-chip. Two devices are required in each channel on each chip (22), a precision comparator, and a storage register. These may be combined with an off-chip analog ram, and an off-chip digital ramp. Certain on-chip performance enhancements are disclosed, which can operate either in the analog mode or the digital mode. One such enhancement is compensating for the voltage offset of each comparator. Another enhancement is reducing the duty cycle of each precision comparator, in order to lower power requirements.
摘要翻译： 公开了一种具有二维光电探测器（24）马赛克的多层Z技术模块（20），其中A / D信号转换的功能在每个片上信道中完成。 为了满足模块的功率和房地产限制，A / D转换电路的绝大部分位于芯片外。 每个芯片（22）的每个通道需要两个器件，一个精密比较器和一个存储寄存器。 这些可能与一个片外模拟RAM和一个片外数字斜坡相结合。 公开了某些片上性能增强功能，可以在模拟模式或数字模式下运行。 一种这样的增强是补偿每个比较器的电压偏移。 另一项增强功能是降低每个精密比较器的占空比，以降低功耗要求。
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公开(公告)号：EP0385979A4
公开(公告)日：1991-06-12
申请号：EP88900618
申请日：1987-10-20
发明人： GO, TIONG, C.
IPC分类号： H05K7/06 , H01L21/70 , H01L23/538 , H01L25/00 , H01L25/04 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/00 , H05K3/36 , H05K7/02 , H05K7/10
CPC分类号： H05K7/023
摘要： A high-density electronic module (24) is disclosed, which is suitable for use as a DRAM, SRAM, ROM, logic unit, arithmetic unit, etc. It is formed by stacking integrated-circuit chips (22), each of which carries integrated circuitry. The chips are glued together, with their leads along one edge, so that all the leads of the stack are exposed on an access plane (28). Where heat extraction augmentation is needed, additional interleaved layers are included in the stacks which have high thermal conductivity, and are electrical insulators. These interleaved layers may carry rerouting electrical conductors. Bonding bumps (31 and 34) are formed at appropriate points on the access plane. A supporting substrate (26), formed of light transparent material, such as silicon, is provided with suitable circuitry and bonding bumps (38 and 42) on its face. A layer of insulation is applied to either the access plane or substrate face, preferably the latter. The bonding bumps on the insulation-carrying surface are formed after the insulation has been applied. The substrate face is placed on the access plane of the stack, their bonding bumps are microscopically aligned, and then bonded together under heat and/or pressure. A layer of thermally conductive (but electrically non-conductive) adhesive material is inserted between the substrate and stack. The substrate and stack combination is then placed and wire bonded in a protective container having leads extending therethrough for external connection.
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8.发明授权
公开(公告)号：EP0204767B1
公开(公告)日：1991-02-27
申请号：EP85906123.6
申请日：1985-11-20
CPC分类号： H01L21/67121 , H01L23/5385 , H01L25/0657 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2924/0002 , H05K3/4611 , Y10T29/49126 , Y10T29/49133 , H01L2924/00
摘要： A method and related fixtures which permit formation of stacks of thin circuitry-carrying layers. The layers terminate in an access plane having a two-dimensional array of closely-spaced electrical leads. The method includes the steps of measuring the thickness of separate chips, selecting groups of chips having appropriate thicknesses, applying appropriate amounts of epoxy between adjacent chips, aligning the chips (and their electrical leads) in the direction parallel to their planes (i.e., the X-axis), and closing the cavity with an end wall which (a) exerts pressure on the stacked chips and epoxy in a direction perpendicular to the chip planes, and (b) establishes a fixed height of the stack in order to align the leads in the Y-axis. The final fixture provides a fixed-size cavity for confining the layers during curing of thermo-setting adhesive which has been applied between each adjacent pair of layers. An initial fixture is provided for accurately measuring the thickness of each layer under substantial layer-flattening pressure. An intermediate fixture is provided for wet stacking the layers prior to their insertion into the final fixture.
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公开(公告)号：EP0116072B1
公开(公告)日：1989-10-11
申请号：EP83902618.4
申请日：1983-07-25
IPC分类号： H03K17/30 , H03K17/693 , H03K17/16
CPC分类号： H03K17/693
摘要： A multiplexer circuit, for use with such signal sources as focal plane detector arrays (20), which contains a large number of parallel branches (24), each of which includes a transconductance MOSFET amplifier and a MOSFET switch of opposite channel polarity from the amplifier (40 and 42, respectively). The amplifier in each branch receives high impedance voltage signals originating from its individual detector (20) and converts them with high power gain into current signals which feed into the common output line (34) whenever the switch (42) in the same branch is turned on. The multiplexer branches, together with the multiplexer control logic, and other electronic devices, are all included on a single IC chip which provides CMOS logic.
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10.发明公开APPARATUS AND METHOD FOR FABRICATING MODULES COMPRISING STACKED CIRCUIT-CARRYING LAYERS 失效用于生产模块，堆叠的集成电路包括在内。
公开(公告)号：EP0204767A1
公开(公告)日：1986-12-17
申请号：EP85906123.0
申请日：1985-11-20
CPC分类号： H01L21/67121 , H01L23/5385 , H01L25/0657 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2924/0002 , H05K3/4611 , Y10T29/49126 , Y10T29/49133 , H01L2924/00
摘要： Un procédé et des pièces correspondantes permettent de former des piles de fines couches porteuses de circuits. Ces couches se terminent par un plan d'accès ayant un agencement bidimensionnel de sorties électriques étroitement serrées. Le procédé comprend les étapes de mesure de l'épaisseur de puces isolées, de sélection de puces ayant l'épaisseur appropriée, d'application de quantités appropriées d'époxy entre des puces adjacentes, d'alignement des puces (et de leurs conducteurs électriques) dans un sens parallèle à leur plan (c'est-à-dire, l'axe X), et de fermeture de la cavité par une paroi terminale qui (a) exerce une pression sur les puces empilées et l'époxy dans un sens perpendiculaire au plan des puces, et (b) établit une hauteur fixe de la pile afin d'aligner les sorties selon l'axe Y. La pièce finale forme une cavité de dimensions fixes pour confiner les couches pendant le durcissement de l'adhésif thermodurcissable appliqué entre chaque paire de couches adjacentes. Une pièce initiale mesure avec précision l'épaisseur de chaque couche sous une pression considérable d'aplatissement de la couche. Une pièce intermédiaire sert à empiler par voie humide les couches avant leur introduction dans la pièce finale.
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