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公开(公告)号：EP2414877B1
公开(公告)日：2020-03-04
申请号：EP10737663.4
申请日：2010-03-29
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公开(公告)号：EP2414888A2
公开(公告)日：2012-02-08
申请号：EP10737662.6
申请日：2010-03-29
IPC分类号： G02F1/025
CPC分类号： G02F1/025 , G02F1/0147 , G02F1/3133 , H01L2224/48091 , H01L2224/48472 , Y10T29/49124 , H01L2924/00014
摘要： Embodiments of an optical device, an array of optical devices, and a technique for fabricating the optical device or the array are described. This optical device is implemented on a substrate (such as silicon), and includes a thermally tunable optical waveguide that has good thermal isolation from its surroundings. In particular, a portion of a semiconductor in the optical device, which includes the optical waveguide, is free standing above a gap between the semiconductor layer and the substrate. By reducing the thermal coupling between the optical waveguide and the external environment, the optical device can be thermally tuned with significantly less power consumption.
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3.发明授权
公开(公告)号：EP2958143B1
公开(公告)日：2017-12-27
申请号：EP15177142.5
申请日：2010-07-09
IPC分类号： H01L25/065 , H01L21/60 , H01L23/28
CPC分类号： H01L25/0657 , H01L23/3121 , H01L23/642 , H01L23/645 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/48 , H01L24/72 , H01L24/90 , H01L25/0652 , H01L29/0657 , H01L2223/6638 , H01L2224/13099 , H01L2224/32145 , H01L2224/32225 , H01L2224/48137 , H01L2224/48157 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06572 , H01L2225/06575 , H01L2225/06589 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01055 , H01L2924/01058 , H01L2924/01067 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19104 , H01L2924/19106 , H01L2924/19107 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A chip package is described (450). This chip package includes a stack of semiconductor dies (110-1,110-2,110-N) or chips that are offset from each other, thereby defining a terrace with exposed pads. A ramp component (112), which is positioned approximately parallel to the terrace, electrically couples to the exposed pads. Mechanical stops (460-1) are formed on respective semiconductor die for mechanical contact between the semiconductor die and the ramp component. The ramp component is electrically coupled to the semiconductor dies using microsprings (114). Consequently, the electrical contacts may have a conductive, a capacitive or, in general, a complex impedance. By removing the need for costly and area-consuming through-silicon vias ( TSV s) in the semiconductor dies, the chip package facilitates chips to be stacked in a manner that provides high bandwidth and low cost.
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公开(公告)号：EP2422270A2
公开(公告)日：2012-02-29
申请号：EP10721863.8
申请日：2010-04-13
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/30112 , G06F9/30138 , G06F9/3838 , G06F9/384
摘要： A register file, in a processor, includes a first plurality of registers of a first size, n-bits. A decoder uses a mapping that divides the register file into a second plurality M of registers having a second size. Each of the registers having the second size is assigned a different name in a continuous name space. Each register of the second size includes a plurality N of registers of the first size, n-bits. Each register in the plurality N of registers is assigned the same name as the register of the second size that includes that plurality. State information is maintained in the register file for each n-bit register. The dependence of an instruction on other instructions is detected through the continuous name space. The state information allows the processor to determine when the information in any portion, or all, of a register is valid.
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公开(公告)号：EP2958143A1
公开(公告)日：2015-12-23
申请号：EP15177142.5
申请日：2010-07-09
IPC分类号： H01L25/065 , H01L21/60 , H01L23/28
CPC分类号： H01L25/0657 , H01L23/3121 , H01L23/642 , H01L23/645 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/48 , H01L24/72 , H01L24/90 , H01L25/0652 , H01L29/0657 , H01L2223/6638 , H01L2224/13099 , H01L2224/32145 , H01L2224/32225 , H01L2224/48137 , H01L2224/48157 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06572 , H01L2225/06575 , H01L2225/06589 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01055 , H01L2924/01058 , H01L2924/01067 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19104 , H01L2924/19106 , H01L2924/19107 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A chip package is described (450). This chip package includes a stack of semiconductor dies (110-1,110-2,110-N) or chips that are offset from each other, thereby defining a terrace with exposed pads. A ramp component (112), which is positioned approximately parallel to the terrace, electrically couples to the exposed pads. Mechanical stops (460-1) are formed on respective semiconductor die for mechanical contact between the semiconductor die and the ramp component. The ramp component is electrically coupled to the semiconductor dies using microsprings (114). Consequently, the electrical contacts may have a conductive, a capacitive or, in general, a complex impedance. By removing the need for costly and area-consuming through-silicon vias ( TSV s) in the semiconductor dies, the chip package facilitates chips to be stacked in a manner that provides high bandwidth and low cost.
摘要翻译： 描述芯片封装（450）。 该芯片封装包括彼此偏移的半导体管芯（110-1,110-2,110-N）或芯片堆叠，从而限定具有暴露焊盘的露台。 位于大致平行于平台的斜坡部件（112）电耦合到暴露的焊盘。 机械止动件（460-1）形成在半导体管芯上，用于半导体管芯和斜坡部件之间的机械接触。 斜坡部件使用微弹簧（114）电耦合到半导体管芯。 因此，电触点可以具有导电性，电容性或通常的复阻抗。 通过消除对半导体管芯中昂贵且占地面积的硅通孔（TSV）的需求，芯片封装便于以提供高带宽和低成本的方式堆叠芯片。
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公开(公告)号：EP2414877A2
公开(公告)日：2012-02-08
申请号：EP10737663.4
申请日：2010-03-29
摘要： Embodiments of an optical device, an array of optical devices, and a technique for fabricating the optical device or the array are described. This optical device is implemented on a substrate (such as silicon), and includes a thermally tunable optical waveguide with a high thermal resistance to the surrounding external environment and a low thermal resistance to a localized heater. In particular, the thermal resistances associated with thermal dissipation paths from a heater in the optical device to an external environment via electrodes and via the substrate are increased, while the thermal resistance between the optical waveguide and the heater is decreased. The heater element consists of a doped semiconductor layer with a rib waveguide (424) on top embedded in a surrounding cladding layer (416) having regions of high doping for improving electrical and termal contact between the electrode (418-1, 418-3) and via material (418-2, 418-4, 420-2, 420-1) and the heater part, (426-2, 422, 426-1).
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公开(公告)号：EP2457253A1
公开(公告)日：2012-05-30
申请号：EP10737694.9
申请日：2010-07-09
IPC分类号： H01L25/065 , H01L23/00 , H01L23/28
CPC分类号： H01L25/0657 , H01L23/3121 , H01L23/642 , H01L23/645 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/48 , H01L24/72 , H01L24/90 , H01L25/0652 , H01L29/0657 , H01L2223/6638 , H01L2224/13099 , H01L2224/32145 , H01L2224/32225 , H01L2224/48137 , H01L2224/48157 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06572 , H01L2225/06575 , H01L2225/06589 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01055 , H01L2924/01058 , H01L2924/01067 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19104 , H01L2924/19106 , H01L2924/19107 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A chip package is described. This chip package includes a stack of semiconductor dies or chips that are offset from each other, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, electrically couples to the exposed pads. For example, the ramp component may be electrically coupled to the semiconductor dies using: microsprings, an anisotropic film, and/or solder. Consequently, the electrical contacts may have a conductive, a capacitive or, in general, a complex impedance. Furthermore, the chips and/or the ramp component may be positioned relative to each other using a ball-and-pit alignment technique. By removing the need for costly and area-consuming through-silicon vias (TSVs) in the semiconductor dies, the chip package facilitates chips to be stacked in a manner that provides high bandwidth and low cost.
摘要翻译： 描述芯片封装（450）。 该芯片封装包括彼此偏移的半导体管芯（110-1,110-2,110-N）或芯片堆叠，从而限定具有暴露焊盘的露台。 位于大致平行于平台的斜坡部件（112）电耦合到暴露的焊盘。 机械止动件（460-1）形成在半导体管芯上，用于半导体管芯和斜坡部件之间的机械接触。 斜坡部件使用微弹簧（114）电耦合到半导体管芯。 因此，电触点可以具有导电性，电容性或通常的复阻抗。 通过消除对半导体管芯中昂贵且占地面积的硅通孔（TSV）的需求，芯片封装便于以提供高带宽和低成本的方式堆叠芯片。
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