公开(公告)号：EP3413344A2

公开(公告)日：2018-12-12

申请号：EP18171767.9

申请日：2018-05-11

申请人： HE System Electronic GmbH & Co. KG

发明人： Münch, Dagmar ,  Reulein, Timo ,  Kastner, Jürgen ,  Fuchs, Martin ,  Römisch, Maximilian ,  Pröll, Peter

IPC分类号： H01L23/34 ,  H01L23/488 ,  H01L25/07

CPC分类号： H01L24/41 ,  H01L23/34 ,  H01L23/495 ,  H01L24/37 ,  H01L24/40 ,  H01L25/072 ,  H01L2224/32227 ,  H01L2224/3701 ,  H01L2224/37012 ,  H01L2224/37013 ,  H01L2224/40145 ,  H01L2224/40147 ,  H01L2224/40227 ,  H01L2224/4103 ,  H01L2224/41052 ,  H01L2224/73263 ,  H01L2924/19104 ,  H01L2924/00012

摘要： Die zu Grunde liegende Erfindung betrifft insbesondere ein Verbindungselement (1), insbesondere Bondelement, umfassend
- einen ersten Verbindungsbereich (11), insbesondere Verbindungsfläche, zur Ausbildung und/oder Herstellung einer insbesondere elektrisch leitenden Verbindung und/oder mechanischen Kopplung und/oder Fixierung eines ersten Bauelements (12), insbesondere eines Leistungshalbleiter-Bauelements, und des Verbindungselements (1), über den/die das Verbindungselement (1) mit dem ersten Bauelement (12) verbunden oder verbindbar ist,
- einen zweiten Verbindungsbereich (13), insbesondere Verbindungsfläche, zur insbesondere elektrisch leitenden Fixierung und/oder Anbindung und/oder Anbringung und/oder Kontaktierung des Verbindungselements an ein zweites Bauelement (14), insbesondere einen ersten Schaltungsträger oder eine Leiterbahn, über den/die das Verbindungselement (1) mit dem zweiten Bauelement (14) verbunden oder verbindbar ist,
- einen dritten Verbindungsbereich (15), insbesondere Verbindungsfläche, zur insbesondere elektrisch leitenden Anbringung und/oder Anbindung und/oder Fixierung eines dritten Bauelements (2), insbesondere eines zweiten Schaltungsträgers, und/oder wenigstens eines Kontaktierungselements (20, 30) an das Verbindungselement (1), über den/die das Verbindungselement (1) mit dem dritten Bauelement (2) verbunden oder verbindbar ist,
sowie eine
Anordnung, insbesondere Schaltungsanordnung.

公开(公告)号：EP3389090A1

公开(公告)日：2018-10-17

申请号：EP17166088.9

申请日：2017-04-11

申请人： ABB Schweiz AG ,  Audi AG

发明人： Schuderer, Jürgen ,  Justin, Villard ,  Mohn, Fabian ,  Liu, Chunlei ,  Apelsmeier, Andreas ,  Asam, Johann

IPC分类号： H01L23/49 ,  H01L23/492 ,  H01L23/34 ,  H01L25/07 ,  H01L25/11

CPC分类号： H01L24/48 ,  H01L23/34 ,  H01L24/20 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L25/071 ,  H01L25/074 ,  H01L25/117 ,  H01L2223/6627 ,  H01L2224/29339 ,  H01L2224/32014 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/41174 ,  H01L2224/4824 ,  H01L2224/4826 ,  H01L2224/48491 ,  H01L2224/83101 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/84447 ,  H01L2224/8484 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/10272 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19104 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A power electronics module (10) comprises a substrate (12) with a substrate metallization layer (14), which is separated into conducting areas (16, 18) for providing conducting paths for the power electronics module (10); a semiconductor switch chip (26) bonded with a first power electrode (28) to a first conducting area (18) of the substrate metallization layer (14); a conductor plate (34, 34') bonded to a second power electrode (30) of the semiconductor switch chip (26) opposite to the first power electrode (28); and a gate conductor (40, 40') bonded to a gate electrode (32) of the semiconductor switch chip (26) besides the second power electrode (30); wherein the conductor plate (34, 34') extends to a second conducting area (16) of the substrate metallization layer (14) and the gate conductor (40, 40') runs through an opening (38) in the conductor plate (34, 34') arranged above the gate electrode (32).

公开(公告)号：EP3314650A1

公开(公告)日：2018-05-02

申请号：EP15896532.7

申请日：2015-06-25

申请人： Intel IP Corporation

发明人： WOLTER, Andreas ,  MEYER, Thorsten ,  KNOBLINGER, Gerhard

IPC分类号： H01L25/07 ,  H01L23/48

CPC分类号： H01F17/0033 ,  H01F41/046 ,  H01F2027/2814 ,  H01L23/645 ,  H01L2224/0401 ,  H01L2224/11 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2924/19042 ,  H01L2924/19104

摘要： Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

公开(公告)号：EP2159841B1

公开(公告)日：2017-11-08

申请号：EP09169228.5

申请日：2009-09-02

申请人： Linear Technology Corporation

发明人： Pruitt, David A.

IPC分类号： H01F19/08 ,  H01L23/64 ,  H01L25/07 ,  H01L25/065 ,  H01F27/28 ,  H01F38/14 ,  H01L23/495

CPC分类号： H01F19/08 ,  H01F38/14 ,  H01F2019/085 ,  H01F2027/2814 ,  H01L23/48 ,  H01L23/4952 ,  H01L23/642 ,  H01L23/645 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/072 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/4823 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48491 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/49052 ,  H01L2224/4912 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2224/4943 ,  H01L2224/85455 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/48824

公开(公告)号：EP3104409A3

公开(公告)日：2017-03-01

申请号：EP16166593.0

申请日：2016-04-22

申请人： MediaTek, Inc

发明人： LIN, Tzu-Hung ,  PENG, I-Hsuan ,  HSIAO, Ching-Wen

IPC分类号： H01L23/538 ,  H01L25/16 ,  H01L25/10 ,  H01L21/60 ,  H01L21/56

CPC分类号： H01L25/16 ,  H01L21/568 ,  H01L21/78 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16145 ,  H01L2224/16265 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81815 ,  H01L2224/92124 ,  H01L2224/92225 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/37001 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

摘要： A semiconductor package assembly is provided. The semiconductor package assembly includes a semiconductor package. The semiconductor package includes a semiconductor die (100). A redistribution layer (RDL) structure (230) is disposed on the semiconductor die and is electrically connected to the semiconductor die. An active (140) or passive element (150) is disposed between the semiconductor die and the RDL structure. A molding compound (220) surrounds the semiconductor die and the active or passive element.

摘要翻译： 提供半导体封装组件。 半导体封装组件包括半导体封装。 半导体封装包括半导体管芯（100）。 再分配层（RDL）结构（230）设置在半导体管芯上并与半导体管芯电连接。 在半导体管芯和RDL结构之间设置有源（140）或无源元件（150）。 模制化合物（220）围绕半导体管芯和有源或无源元件。

公开(公告)号：EP3091573A3

公开(公告)日：2017-02-22

申请号：EP16161852.5

申请日：2016-03-23

申请人： MediaTek, Inc

发明人： HSIAO, Ching-Wen ,  LIN, Tzu-Hung ,  PENG, I-Hsuan ,  HSIEH, Tung-Hsien ,  CHANG, Sheng-Ming

IPC分类号： H01L25/16 ,  H01L25/10 ,  H01L23/538 ,  H01L23/34 ,  H01L23/50

CPC分类号： H01L23/3675 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00

摘要： A semiconductor chip package assembly (1) includes a package substrate (200) having a chip mounting surface (200a); a plurality of solder pads (212) disposed on the chip mounting surface; a first dummy pad (211) and a second dummy pad (211) spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask (202) on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a chip package (100) mounted on the chip mounting surface and electrically connected to the package substrate through a plurality of solder balls (250) on respective said solder pads (212); a discrete device (150)having a first terminal (151) and a second terminal (152) disposed between the chip package and the package substrate; a first solder (154) connecting the first terminal with the first dummy pad (211) and the chip package (100); and a second solder (154) connecting the second terminal (152) with the second dummy pad (211) and the chip package (100).

公开(公告)号：EP3131117A1

公开(公告)日：2017-02-15

申请号：EP16182128.5

申请日：2016-08-01

申请人： Semtech Corporation

发明人： HO, Kok Khoon ,  CHINNUSAMY, Satyamoorthi

IPC分类号： H01L23/16

CPC分类号： H01L23/5389 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/56 ,  H01L21/78 ,  H01L23/13 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/433 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/17 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05575 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/13013 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16113 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/1713 ,  H01L2224/17181 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/80 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10322 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/3025 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/81

摘要： A semiconductor device has a first substrate. A conductive layer is formed over the first substrate. A first cavity is formed through the first substrate and extending to the conductive layer. A first semiconductor die including a plurality of first interconnect structures is disposed in the first cavity. A second substrate is disposed over the first substrate. A second cavity is formed through second substrate. A second semiconductor die including a plurality of second interconnect structures is disposed in the second cavity. A discrete device or third semiconductor die is disposed over the second semiconductor die. A plurality of third interconnect structures is formed between the second substrate and discrete device or third semiconductor die. The first, second, and third interconnect structures are reflowed simultaneously. An encapsulant is deposited over and around the first semiconductor die, the second semiconductor die, and the discrete device or third semiconductor die.

摘要翻译： 一种半导体器件具有第一衬底。 的导电层被形成在所述第一基底上。 第一腔体通过所述第一基片形成，并且延伸到所述导电层。 第一半导体包括第一互连结构的中的多个第一腔体被设置。 第二基板被设置在所述第一基底上。 的第二空腔，通过第二基片形成。 第二半导体包括第二互连结构的中的多个第二腔体被设置。 分立器件或第三半导体管芯设置在所述第二半导体那个。 第三互连结构中的多个设置在第二基底和分立器件或第三半导体那之间形成。 第一，第二和第三互连结构被同时回流。 密封剂沉积上方和周围的第一半导体是，所述第二半导体是，和分立器件或第三半导体那个。

公开(公告)号：EP3046148A1

公开(公告)日：2016-07-20

申请号：EP15170129.9

申请日：2011-12-09

申请人： Analog Devices, Inc.

发明人： O'Donnell, Alan ,  Iriarte, Santiago ,  Murphy, Mark ,  Lyden, Colin G. ,  Casey, Gary ,  English, Eoin

IPC分类号： H01L25/16

CPC分类号： G01N27/226 ,  B81B7/00 ,  B81B7/007 ,  B81B2201/0214 ,  G01N27/26 ,  G01N27/4148 ,  H01F17/00 ,  H01F17/04 ,  H01L21/82 ,  H01L23/3677 ,  H01L23/38 ,  H01L23/473 ,  H01L23/481 ,  H01L23/58 ,  H01L24/05 ,  H01L24/13 ,  H01L24/48 ,  H01L24/94 ,  H01L25/16 ,  H01L25/167 ,  H01L27/0694 ,  H01L27/14 ,  H01L27/15 ,  H01L28/00 ,  H01L28/10 ,  H01L28/20 ,  H01L28/60 ,  H01L28/82 ,  H01L28/86 ,  H01L28/90 ,  H01L31/0392 ,  H01L31/0525 ,  H01L31/0547 ,  H01L31/056 ,  H01L31/06 ,  H01L35/00 ,  H01L35/28 ,  H01L35/30 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0556 ,  H01L2224/0557 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48265 ,  H01L2225/06531 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H02S10/10 ,  H02S40/38 ,  Y02E10/50 ,  Y02E10/52 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05552 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

摘要翻译： 本发明的实施例提供了一种集成电路系统，其包括在半导体管芯的前侧制造的第一有源层和在半导体管芯的背面上的第二预制层，并且具有体现在其中的电气部件，其中电气部件 包括至少一个分立的无源部件。 集成电路系统还包括耦合第一有源层和第二预制层的至少一个电路径。

公开(公告)号：EP3014742A1

公开(公告)日：2016-05-04

申请号：EP14818632.3

申请日：2014-06-18

申请人： Intel IP Corporation

发明人： DROEGE, Guido ,  SCHAEFER, Andre ,  ZILLMANN, Uwe

IPC分类号： H02J50/00 ,  H02J7/00 ,  H01F38/14

CPC分类号： H02J1/00 ,  G05F1/618 ,  G11C5/025 ,  G11C5/14 ,  G11C5/147 ,  G11C7/00 ,  H01L2924/19042 ,  H01L2924/19104 ,  H02M1/088

摘要： An apparatus such as heterogeneous device includes at least a first die and a second die. The apparatus further includes a first inductive element, a second inductive element, and switch control circuitry. The switch control circuitry is disposed in the first die. The switch control circuitry controls current through the first inductive element to produce a first voltage. The first voltage powers the first die. The second inductive element is coupled to the first inductive element. The second inductive element produces a second voltage to power the second die. The first die and second die can be fabricated in accordance with different technologies and in which the first die and second die withstand different maximum voltages. A magnitude of the first voltage can be greater than a magnitude of the second voltage.

公开(公告)号：EP2958143A1

公开(公告)日：2015-12-23

申请号：EP15177142.5

申请日：2010-07-09

申请人： Oracle America, Inc. formerly known as Sun Microsystems, Inc.

发明人： DROST, Robert J ,  MITCHELL, James G. ,  DOUGLAS, David C.

IPC分类号： H01L25/065 ,  H01L21/60 ,  H01L23/28

CPC分类号： H01L25/0657 ,  H01L23/3121 ,  H01L23/642 ,  H01L23/645 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/48 ,  H01L24/72 ,  H01L24/90 ,  H01L25/0652 ,  H01L29/0657 ,  H01L2223/6638 ,  H01L2224/13099 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48137 ,  H01L2224/48157 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01067 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/19106 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package is described (450). This chip package includes a stack of semiconductor dies (110-1,110-2,110-N) or chips that are offset from each other, thereby defining a terrace with exposed pads. A ramp component (112), which is positioned approximately parallel to the terrace, electrically couples to the exposed pads. Mechanical stops (460-1) are formed on respective semiconductor die for mechanical contact between the semiconductor die and the ramp component. The ramp component is electrically coupled to the semiconductor dies using microsprings (114). Consequently, the electrical contacts may have a conductive, a capacitive or, in general, a complex impedance. By removing the need for costly and area-consuming through-silicon vias ( TSV s) in the semiconductor dies, the chip package facilitates chips to be stacked in a manner that provides high bandwidth and low cost.

摘要翻译： 描述芯片封装（450）。 该芯片封装包括彼此偏移的半导体管芯（110-1,110-2,110-N）或芯片堆叠，从而限定具有暴露焊盘的露台。 位于大致平行于平台的斜坡部件（112）电耦合到暴露的焊盘。 机械止动件（460-1）形成在半导体管芯上，用于半导体管芯和斜坡部件之间的机械接触。 斜坡部件使用微弹簧（114）电耦合到半导体管芯。 因此，电触点可以具有导电性，电容性或通常的复阻抗。 通过消除对半导体管芯中昂贵且占地面积的硅通孔（TSV）的需求，芯片封装便于以提供高带宽和低成本的方式堆叠芯片。