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公开(公告)号：EP1194813A1
公开(公告)日：2002-04-10
申请号：EP00904300.1
申请日：2000-01-11
IPC分类号： G03F1/00
摘要： A method for forming a photomask includes providing a transparent substrate and forming an opaque layer over at least a first portion of the transparent substrate. The opaque layer is patterned to define a mask pattern and expose at least a second portion of the transparent substrate. The second portion is etched to define a phase shifting region. The width of the phase shifting region defines a critical dimension. The critical dimension is measured, and the phase shifting region is etched based on the critical dimension to undercut the optically opaque layer. A photomask includes a transparent substrate and a phase shitting region defined in the transparent substrate. The phase shifting region includes sloped sidewalls having a slope of less than about 85°.
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公开(公告)号：EP1192544A1
公开(公告)日：2002-04-03
申请号：EP00935982.9
申请日：2000-05-16
IPC分类号： G06F11/10
CPC分类号： G11B20/18 , G06F11/1008
摘要： An error correction circuit and method for a memory device use an error correcting block code such as a Hamming code to detect and correct errors, if any, in the data bytes. The error correction circuit and method are capable of improving the speed of error correction to reduce delays in the external data access time.
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3.发明公开
公开(公告)号：EP1180285A1
公开(公告)日：2002-02-20
申请号：EP99967237.1
申请日：1999-12-07
IPC分类号： H04L12/44
CPC分类号： H04L49/351 , H04L49/205 , H04L49/3027 , H04L49/352 , H04L49/354 , H04L69/14
摘要： A network switch configured for switching data packets across multiple ports uses an address table to generate frame forwarding information. A decision-making engine checks the frame forwarding information to determine whether the frame is to be forwarded on a port that is part of a trunk. When the frame is to be output on a trunk port, the decision-making engine determines the port on which to transmit the frame.
摘要翻译： 配置为跨多个端口交换数据分组的网络交换机使用地址表来生成帧转发信息。 决策引擎检查帧转发信息以确定帧是否要在作为中继线一部分的端口上转发。 当帧要在中继端口上输出时，决策引擎确定要在其上发送帧的端口。
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4.发明公开CONSERVATION OF SYSTEM MEMORY BANDWIDTH AND CACHE COHERENCY MAINTENANCE USING MEMORY CANCEL MESSAGES 审中-公开保存系统的内存带宽和保持高速缓存一致性SPEICHERANNULIERUNGSNACHRICHTEN
公开(公告)号：EP1141838A1
公开(公告)日：2001-10-10
申请号：EP99944008.4
申请日：1999-08-26
发明人： KELLER, James, B.
IPC分类号： G06F12/08
CPC分类号： G06F12/0828 , G06F12/0813 , G06F2212/2542
摘要： A messaging scheme that conserves system memory bandwidth and maintains cache coherency during a victim block write operation in a multiprocessing computer system (10) is described. A target node (72) receives a memory cancel response corresponding to a transaction, and aborts processing of the transaction in response to the memory cancel response. In one embodiment, the transaction is a victim block write and the memory cancel response is received from a source node (70). In another embodiment, the transaction is a read operation and the memory cancel response is received from a different node (76) having a modified copy of the data addressed by the read operation.
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公开(公告)号：EP1203402A1
公开(公告)日：2002-05-08
申请号：EP00917918.5
申请日：2000-03-14
IPC分类号： H01L21/027 , G03F7/42
CPC分类号： G03F7/425 , G03F7/40 , G03F7/42 , H01L21/0274 , H01L21/31133
摘要： A resist removal method provides for analyzing a patterned resist and determining if rework needs to be performed due to the pattern being incorrect. If the pattern is incorrect, the entire upper surface of the patterned resist is exposed to mild UV light. The exposed patterned resist is then subjected to a developer, such as an alkaline bath, such that the exposed patterned resist is dissolved away from the substrate, and such that a new layer of resist can be applied and then patterned.
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6.发明公开NEW METHOD OF FORMING SELECT GATE TO IMPROVE RELIABILITY AND PERFORMANCE FOR NAND TYPE FLASH MEMORY DEVICES 审中-公开新方法选通门从NAND型闪存STORE更高的可靠性和性能的生产
公开(公告)号：EP1198834A1
公开(公告)日：2002-04-24
申请号：EP00943282.4
申请日：2000-06-29
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11529 , H01L27/11546
摘要： In one embodiment, the present invention relates to a method of forming a NAND type flash memory device, involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a core region and a periphery region, the core region including a flash memory cell area and a select gate area and the periphery region including a high voltage transistor area and low voltage transistor area; depositing a first doped amorphous silicon layer over at least a portion of the first oxide layer; depositing a dielectric layer over at least a portion of the first doped amorphous silicon layer; removing portions of the first oxide layer, the first doped amorphous silicon layer, and the dielectric layer in the select gate area of the core region and the high voltage transistor area and the low voltage transistor area the periphery region; growing a second oxide layer over at least a portion of the substrate in the select gate area of the core region and the high voltage transistor area and the low voltage transistor area the periphery region; removing portions of the second oxide layer in the select gate area of the core region and the low voltage transistor area the periphery region; growing a third oxide layer over at least a portion of the substrate in the select gate area of the core region and the low voltage transistor area of the periphery region; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer, the second oxide layer and the third oxide layer; and forming a flash memory cell in the flash memory cell area of the core region, a select gate transistor in the select gate area of the core region, a low voltage transistor in the low voltage transistor area of the periphery region, and a high voltage transistor in the high voltage transistor area of the periphery region.
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7.发明公开METHOD FOR FABRICATION OF A LOW RESISTIVITY MOSFET GATE WITH THICK METAL SILICIDE ON POLYSILICON 审中-公开低MOSFET栅极的制备过程中，通过厚的金属硅化物多晶硅
公开(公告)号：EP1181711A2
公开(公告)日：2002-02-27
申请号：EP00917912.8
申请日：2000-03-13
IPC分类号： H01L21/00
CPC分类号： H01L29/66507 , H01L21/28052 , H01L29/4933 , H01L29/66545 , H01L29/6659
摘要： The present invention is a method for fabricating a gate of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with the gate having low resistivity. The MOSFET has a drain region, a source region, and a channel region fabricated within a semiconductor substrate, and the MOSFET initially has a gate comprised of a first metal silicide on polysilicon disposed on a gate dielectric over the channel region. Generally, the method of the present invention includes a step of depositing a first dielectric layer over the drain region, the source region, and the gate of the MOSFET. The present invention also includes steps of polishing down the first dielectric layer over the drain region and the source region, and of polishing down the first dielectric layer over the gate until the first metal silicide or the polysilicon of the gate is exposed. The present invention further includes the step of depositing a metal over the first metal silicide if the first metal silicide is exposed or over the polysilicon if the polysilicon is exposed, and of performing a silicidation anneal to form a second metal silicide over a remaining portion of the polysilicon. The thickness of the second metal silicide is greater than the thickness of the first metal silicide. In this manner, the gate of the present invention has low resistivity since a relatively thick layer of metal silicide is formed on the remaining portion of the polysilicon. In addition, with the present invention, the remaining portion of the polysilicon has a sufficient thickness such that a threshold voltage of the MOSFET is not substantially affected by the second metal silicide disposed on top of the remaining portion of the polysilicon.
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公开(公告)号：EP1145308A1
公开(公告)日：2001-10-17
申请号：EP99965057.5
申请日：1999-11-29
发明人： CAGNINA, Salvatore, F. , FANG, Hao , WANG, John, Jianshi , CHANG, Kent, Kuohua , HIGASHITANI, Masaaki
IPC分类号： H01L21/8239 , H01L21/8247
CPC分类号： H01L27/11526 , H01L27/11546
摘要： A semiconductor process for fabricating NAND type flash memory devices in a first embodiment includes step which can be performed on a production line which manufactures NOR type flash memory products. A NAND flash memory fabrication process according to a second embodiment simplifies the process and uses fewer masks, thus reducing costs and errors to produce higher yields.
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公开(公告)号：EP1183652A1
公开(公告)日：2002-03-06
申请号：EP00936354.0
申请日：2000-05-25
申请人： Broadcom Corporation
发明人： POSNIEWSKI, Shannon , KOCHUBIEVSKI, Vadim , NISSEN, Glenn , MOVSHOVICH, Aleksandr , LEWIS, Michael, C.
IPC分类号： G06T15/20
CPC分类号： G06T15/04
摘要： A method and system for processing textures for a graphical image on a display is disclosed. The graphical image includes a plurality of polygons. Each of the plurality of polygons includes at least one fragment. The fragment includes at least one texture and a w-value for the fragment. Each polygon has a plurality of vertices, a display area, and a texture space area. Each of the vertices has a vertex w-value. The at least one texture is associated with at least one MIP map. The MIP map includes a plurality of MIP map levels. The method and system include determining a selection value for each fragment of a polygon of the plurality of polygons. The selection value includes 1/2 multiplied by the base two logarithm of the texture area divided by the display area and divided by the product of the vertex w-values for each of the plurality of vertices. The selection value also includes 3/2 multiplied by the base two logarithm of the w-value for each of the at least one fragment. The selection value also includes a MIP map bias. The method and system also include selecting at least one of the plurality of MIP map levels map for each fragment based on the selection value for each fragment.
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10.发明公开
公开(公告)号：EP1201043A1
公开(公告)日：2002-05-02
申请号：EP00914534.3
申请日：2000-02-07
申请人： Legerity, Inc.
发明人： GERSHON, Eugen
CPC分类号： H04M11/062 , H04B3/46 , H04M1/24 , H04M3/30
摘要： The present invention provides for an apparatus and a method for testing and evaluating a transmission line. A set of command and data signals is received through an input/output interface (410). The command and data signals from the input/output interface (410) are processed for controlling at least one relay (430). At least one switch is activated for testing a transmission signal line using the relay (430). The transmission signal line is tested based upon the activated switch. The present invention further comprises an apparatus for testing and evaluating a transmission line, comprising a network interface device (110) capable of implementing one or more tests on the transmission line.
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