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    CMOS BUFFER CIRCUIT HAVING POWER-DOWN FEATURE
    1.
    发明公开
    CMOS BUFFER CIRCUIT HAVING POWER-DOWN FEATURE 失效
    关闭电源CMOS缓冲电路

    公开(公告)号：EP0846371A1

    公开(公告)日：1998-06-10

    申请号：EP96928894.0

    申请日：1996-08-23

    Applicant: HAL COMPUTER SYSTEMS, INC.

    Inventor： MONTOYE, Robert, K. ,  ZASIO, John, J.

    IPC: G01R31 ,  H03K19

    CPC classification number: H03K19/00315

    Abstract: The gate of a P-channel pull-up transistor (MP1) connected between an input node (A) and a supply voltage (VDD) in a buffer circuit (21) is coupled to a test node (22). An N-channel pull-down transistor (MNpd) is connected between the input node (A) and ground and has a gate connected to the test node (22). A logic low signal provided to the test node (22) allows the circuit (21) to operate normally. During test mode, a logic high signal is provided to the test node (22) to turn off the P-channel pull-up transistor (MP1) and thus prevent DC current flow in the circuit via the pull-up transistor (MP1). This logic high signal also turns on the pull-down transistor (MNpd) and, by shorting the input node (A) to ground potential, prevents any other DC crossover currents from flowing in the circuit (21).

    CROSSBAR SWITCH AND METHOD WITH REDUCED VOLTAGE SWING AND NO INTERNAL BLOCKING DATA PATH
    2.
    发明公开
    CROSSBAR SWITCH AND METHOD WITH REDUCED VOLTAGE SWING AND NO INTERNAL BLOCKING DATA PATH 失效
    CROSS切换开关和方法，限制电压摆幅和阻断免费教育

    公开(公告)号：EP0840971A2

    公开(公告)日：1998-05-13

    申请号：EP97908726.0

    申请日：1997-02-20

    Applicant: FUJITSU LIMITED

    Inventor： MU, Albert ,  LARSON, Jeffrey, D.

    IPC: H04L12 ,  H04Q3

    CPC classification number: H04Q3/523 ,  H04L49/101 ,  H04L49/205 ,  H04L49/25 ,  H04L49/254 ,  H04L49/3018

    Abstract: A switch system and method transfer a data packet from a source data port to one or more destination data ports through a switch. The system comprises a source input buffer, a first and a second source input path, a first and a second output path and at least one crosspoint circuit. The source input buffer includes a first and a second data section. The first and the second data sections are coupled to the first and the second input paths respectively. The first and the second input paths couple through the crosspoint circuits at each intersection with the first and the second output paths. The method includes loading the data packets into data sections of an input buffer, transferring each data packet across an input path dedicated for each data section, transmitting each data packet over its input path, and switching the data from the input path to the output path based on a voltage differential. A crosspoint circuit in the switch system includes a first and a second reduced voltage swing line, a first and a second transistor circuit for each data input path and a sense amplifier for a data port. The first reduced voltage swing line is coupled to the first transistor circuit, the second reduced voltage swing line is coupled to the second transistor circuit and both reduced voltage swing lines are connected to the sense amplifier. The method of the unit comprises the steps of charging a first and a second reduced voltage swing line to a predetermined voltage, discharging the voltage from the first reduced voltage swing line, maintaining the voltage in the second voltage line, receiving a clock signal at the sense amplifier, and generating an output signal based on a voltage differential between the voltage lines.

    CLOCKED SENSE AMPLIFIER WITH POSITIVE SOURCE FEEDBACK
    3.
    发明公开
    CLOCKED SENSE AMPLIFIER WITH POSITIVE SOURCE FEEDBACK 失效
    与正源极反馈主频检测放大器

    公开(公告)号：EP0830683A1

    公开(公告)日：1998-03-25

    申请号：EP97906538.0

    申请日：1997-02-12

    Applicant: HAL COMPUTER SYSTEMS, INC.

    Inventor： MU, Albert

    IPC: G11C11 ,  G11C7

    CPC classification number: G11C7/065 ,  G11C7/062

    Abstract: A differential sense amplifier includes positive feedback cross coupling to control operation in one mode as a differential sense amplifier and in another mode as a latch to control a data-latching load. Circuit nodes are precharged and equalized in response to applied enable signal.

    METHOD AND APPARATUS FOR ROTATING ACTIVE INSTRUCTIONS IN A PARALLEL DATA PROCESSOR
    4.
    发明公开
    METHOD AND APPARATUS FOR ROTATING ACTIVE INSTRUCTIONS IN A PARALLEL DATA PROCESSOR 失效
    方法和装置AKTIEVEN命令的并行数据处理器旋转

    公开(公告)号：EP0829045A1

    公开(公告)日：1998-03-18

    申请号：EP96919024.0

    申请日：1996-05-31

    Applicant: HAL COMPUTER SYSTEMS, INC.

    Inventor： SAVKAR, Sunil ,  SHEBANOW, Michael, C. ,  SHEN, Gene, W. ,  SAJJADIAN, Farnad

    IPC: G06F9

    CPC classification number: G06F9/382 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

    Abstract: In a microprocessor, apparatus and method coordinate the fetch and issue of instructions by rotating multiple, fetched instructions into an issue order prior to issuance and dispatching selected of the issue ordered instructions. The rotate and dispatch block including a mixer for mixing newly fetched instructions with previously fetched and unissued instructions in physical memory order, a mix and rotate device for rotating the mixed instructions into issue order, an instruction latch for holding the issue ordered instructions prior to dispatch, and an unrotate device for rotating non-issued instructions from issue order to physical memory order prior to mixing with newly fetched instructions. During the fetch cycle, multiple instructions are simultaneously fetched from storage in physical memory order and rotated into a PC-related issue order within the rotate and dispatch block. During the next clock cycle, selected ones of the previously fetched and rotated instructions enter the issue cycle, a new set of instructions are fetched in physical memory order, the previously fetched and rotated instructions which were not issued are rearranged into physical memory order and mixed in physical memory order with the newly fetched instructions, together all fetched and non-issued instructions are rotated into issue order prior to the next issue cycle, and so forth until all instructions have passed through the pipeline.

    LEARNING PROCESSING SYSTEM OF NETWORK STRUCTURE DATA PROCESSING UNIT
    7.
    发明公开
    LEARNING PROCESSING SYSTEM OF NETWORK STRUCTURE DATA PROCESSING UNIT 失效
    EERER NETZWERKSTRUKTUR-DATENVERARBEITUNGSEINHEIT的文章VERARBEITUNGSSYSTEM。

    公开(公告)号：EP0388474A1

    公开(公告)日：1990-09-26

    申请号：EP89910193.0

    申请日：1989-09-11

    Applicant: FUJITSU LIMITED

    Inventor： WATANABE, Nobuo ,  KIMOTO, Takashi 1-4-1-210, Nishi-kubo-cho ,  KAWAMURA, Akira ,  MASUOKA, Ryusuke ,  ASAKAWA, Kazuo Aberia 3-403 2-10-1, Miyamae-daira

    IPC: G06N3

    CPC classification number: G06N3/084 ,  G06N3/04

    Abstract: A basic unit for obtaining an output is constituted by multiplying a number of inputs by weights, totaling the results of multiplications to obtain a product sum and obtaining the output from this product sum by use of a threshold function. A hierarchical network consisting of an input layer, an intermediate layer and an output layer is constituted by use of such a basic unit. The hierarachical network conducts learning by determining the updating quantity of the weights from errors between the output signals obtained from the output layer for a number of inputs and teacher's signals representing the values which the output signals should take on, in accordance with a back-propagation method in order to obtain the weight value which keeps the sum of error values within a predetermined allowance range. In learning of such a hierarachical network, the updating quantity of the weight to be obtained at the time of the current weight updating cycle is determined in consideration of the updating quantity of the weight obtained at the time of ne cycle earlier updating cycle than the last updating cycle in addition to the updating quantity of the weight determined at the time of the last weight updating cycle.

    Abstract translation: 用于获得输出的基本单元是通过将输入的数量乘以权重组合，将乘法结果合计以获得乘积和，并通过使用阈值函数从该乘积和获得输出。 由输入层，中间层和输出层构成的分层网络由这种基本单元构成。 分级网络通过根据输入信号从输出层获得的输出信号和输出信号应该承受的值的教师信号之间的错误确定权重的更新量来进行学习，根据反向传播 方法，以获得将误差值之和保持在预定容限范围内的权重值。 在学习这样的层次性网络时，考虑到在更新循环更新周期之前获得的权重的更新量，比当前权重更新周期更新时的更新量要重新确定 更新周期以及在最后加权更新周期时确定的权重的更新量。

    X-RAY IMAGING PLATE, METHOD FOR PRODUCING X-RAY IMAGING PLATE, PHOSPHOR OF PHOTOSTIMULATED LUMINESCENCE MATERIAL, AND METHOD FOR PRODUCING PHOSPHOR OF PHOTOSTIMULATED LUMINESCENCE MATERIAL
    8.
    发明公开
    X-RAY IMAGING PLATE, METHOD FOR PRODUCING X-RAY IMAGING PLATE, PHOSPHOR OF PHOTOSTIMULATED LUMINESCENCE MATERIAL, AND METHOD FOR PRODUCING PHOSPHOR OF PHOTOSTIMULATED LUMINESCENCE MATERIAL 失效
    XRAY丝网处理用于制造用于生产其的一样，光激励荧光粉和方法。

    公开(公告)号：EP0362405A1

    公开(公告)日：1990-04-11

    申请号：EP89903266.0

    申请日：1989-03-07

    Applicant: FUJITSU LIMITED

    Inventor： HIRANO, Hiroshi 3462, Noborito ,  IWASE, Nobuhiro Fujitsu-Atsugiryo ,  KOSHINO, Nagaaki 103-1-302, Higashikibogaoka

    IPC: C09K11 ,  G21K4

    CPC classification number: C09K11/7739 ,  C09K11/628 ,  C09K11/7705 ,  C09K11/7728 ,  C09K11/7731 ,  C09K11/7733 ,  G21K4/00

    Abstract: Améliorations relatives à une plaque sensible aux rayons X, à un procédé de production de cette plaque, à une substance luminescente photostimulée et à un procédé de production de cette substance, comprenant (1) un moyen permettant de n'utiliser qu'une étape de calcination ou d'enlever un substrat d'une feuille de substance luminescente afin d'améliorer l'intensité de luminescence, (2) un moyen permettant d'ajouter un ou plusieurs films résistant à l'humidité sur le film de protection ordinaire, (3) un moyen permettant d'éliminer un liant contenu dans la substance luminescente par la réduction en cendres, afin d'améliorer l'intensité de luminescence, (4) un moyen permettant d'effectuer la calcination de manière à obtenir un semi-produit concassé par une plaque de quartz pour compenser un gauchissement d'une plaque sensible aux rayons X, (5) un moyen permettant d'utiliser au moins de l'hélium comme gaz réducteur dans le but de convertir entièrement l'europium tervalent contenu dans le matériau brut d'une substance luminescente en europium bivalent, de manière à améliorer l'intensité de luminescence, et (6) un moyen permettant d'utiliser un composé complexe contenant des halogénures de métaux alcalino-terreux et un sulfure d'un métal alcalino-terreux, par exemple BaCl2-xBaBr2-yCas:zEu2+ et autres pour accroître l'intensité de luminescence dans la plage de longueurs d'ondes comprises entre 650 et 850 nm, de manière à permettre l'utilisation d'un laser à semi-conducteur comme lumière d'excitation.

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