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公开(公告)号：EP1632952A3
公开(公告)日：2008-01-23
申请号：EP05254988.8
申请日：2005-08-11
发明人： Edan, Mori , Sofer, Yair , Grossgold, Meir , Eliyahu, Ron
IPC分类号： G11C16/20
CPC分类号： G11C16/20
摘要： A system and a method for operating a non-volatile memory (NVM) device including a micro-controller adapted to control peripheral circuitry associated with an NVM array. The method includes providing at least one operation command to the micro-controller of the NVM device and applying operating signals to peripheral circuitry of the NVM device to operate the NVM array based on at least one operation command. The system includes: a NVM device (20) with a NVM array (28) adapted to store data and commands, peripheral circuitry (P 1 ...P n ) adapted to operate the NVM array and a micro-controller (24) adapted to control the peripheral circuitry; and an external device to provide at least one command to the micro-controller of the NVM device.
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公开(公告)号：EP1763080A2
公开(公告)日：2007-03-14
申请号：EP06120354.3
申请日：2006-09-08
发明人： Lusky, Eli , Eitan, Boaz
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11568 , H01L27/115
摘要： A non-volatile memory device includes a plurality of word line areas each separated from its neighbor by a contact area, an oxide-nitride-oxide (ONO) layer within the word line areas and at least partially within the contact areas and protective elements generated when spacers are formed in the periphery area, to protect silicon under the ONO layer in the contact areas A non-volatile memory device includes a plurality of word line areas each separated from is neighbor by a contact area and bit line oxides whose height is at least a quarter of the distance between neighboring bit line oxides.
摘要翻译： 非易失性存储器件包括多个字线区域，每个字线区域与其相邻部分由接触区域分开，字线区域内的氧化物 - 氧化物 - 氧化物（ONO）层和至少部分地在接触区域内产生的保护元件 当在周边区域中形成间隔物时，为了保护接触区域内的ONO层下的硅，非易失性存储器件包括多个字线区域，每个字线区域与接触区域相邻，位线高度位于 相邻位线氧化物之间的距离最少四分之一。
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公开(公告)号：EP1755128A2
公开(公告)日：2007-02-21
申请号：EP06118948.6
申请日：2006-08-15
发明人： Shappir, Assaf , Cohen, Guy , Lusky, Eli
IPC分类号： G11C16/26
CPC分类号： G11C16/28 , G11C16/04 , G11C16/0475 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/28 , G11C29/50 , G11C29/50004
摘要： A method includes changing a read reference level for reading a group of memory cells as a function of changes in a threshold voltage distribution of a different group of memory cells. The changing step includes determining a history read reference level of a group of history cells associated with a group of memory cells of a non-volatile memory cell array, allowing correct reading of the group of history cells, selecting a memory read reference level according to the first read reference level, and reading the non-volatile memory array cells.
摘要翻译： 一种方法包括根据不同组存储器单元的阈值电压分布的改变来改变用于读取一组存储器单元的读取参考电平。 改变步骤包括确定与非易失性存储器单元阵列的一组存储器单元相关联的一组历史存储单元的历史读取参考电平，允许正确读取该组历史存储单元，根据 第一读取参考电平以及读取非易失性存储器阵列单元。
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4.发明公开A method of erasing non-volatile memory cells 审中-公开Verfahren zumLöschennichtflüchtigerSpeicherzellen
公开(公告)号：EP1755127A2
公开(公告)日：2007-02-21
申请号：EP06118949.4
申请日：2006-08-15
发明人： Lusky, Eli , Eitan, Boaz
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C16/344 , G11C16/3445
摘要： A method includes determining groups of rows to erase together in order to minimize the margin loss associated with bake after a large number of program and erasure cycles. The method alternatively includes determining groups of rows to erase together to minimize the width of a resultant erase threshold voltage distribution, erasing the groups together, stopping erasure of a group when the group is erase verified and performing the step of erasing on those groups which were not previously erase verified.
摘要翻译： 一种方法包括确定要一起擦除的行组，以便在大量编程和擦除循环之后最小化与烘烤相关的裕度损失。 所述方法或者包括确定一组行以擦除在一起以最小化所得到的擦除阈值电压分布的宽度，擦除组在一起，当组被擦除验证时停止擦除组，并且执行擦除步骤 以前没有擦除验证。
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公开(公告)号：EP1727204A2
公开(公告)日：2006-11-29
申请号：EP06114481.2
申请日：2006-05-24
发明人： Bloom, Ilan
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/1052
摘要： A method for embedding non-volatile memories with logic circuitry, without changing performance of both the logic circuitry and the NVM elements (and/or without changing a sequence of manufacturing steps for both the logic circuitry and the NVM elements). The embedding process includes insertion of NVM device and anay process steps into an existing logic CMOS process in a way that maintains the CMOS performance, thereby enabling use of existing circuit libraries. The NVM may thus be combined with the high-speed low-voltage CMOS without any performance or reliability penalty.
摘要翻译： 一种用逻辑电路嵌入非易失性存储器的方法，而不改变逻辑电路和NVM元件的性能（和/或不改变逻辑电路和NVM元件的制造步骤序列）。 嵌入过程包括以维持CMOS性能的方式将NVM器件插入到现有的逻辑CMOS工艺中，从而使得能够使用现有的电路库。 因此，NVM可以与高速低压CMOS组合，而没有任何性能或可靠性损失。
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公开(公告)号：EP1708265A2
公开(公告)日：2006-10-04
申请号：EP05253514.3
申请日：2005-06-08
发明人： Shor, Joseph S , Maayan, Eduardo , Betser, Yoram
CPC分类号： H01L27/0811
摘要： A capacitor including a first active layer capacitively coupled to a second active layer, the second active layer being capacitively coupled to a third layer, the third layer being capacitively coupled to a fourth layer, wherein an anode of the capacitor is connected to one of the first and second active layers, and a cathode of the capacitor is connected to the other one of the first and second active layers, and wherein the third layer is left floating. The fourth layer may be connected to a supply voltage, such as but not limited to, ground.
摘要翻译： 一种电容器，包括电容耦合到第二有源层的第一有源层，所述第二有源层电容耦合到第三层，所述第三层电容耦合到第四层，其中所述电容器的阳极连接到 第一和第二有源层，并且电容器的阴极连接到第一和第二有源层中的另一个，并且其中第三层是浮置的。 第四层可以连接到电源电压，例如但不限于接地。
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公开(公告)号：EP1686592A2
公开(公告)日：2006-08-02
申请号：EP06100507.0
申请日：2006-01-18
发明人： Shappir, Assaf , Eisen, Shai
CPC分类号： G11C16/10 , G06F12/1408 , G11C11/5635 , G11C16/0475 , G11C16/14 , G11C16/16 , G11C16/26 , G11C16/3404 , G11C16/344 , G11C16/3445 , G11C16/349 , G11C2216/18
摘要： A method for erasing memory cells in a memory array, the method including applying an erase pulse to bits of a cell ensemble of a memory cell array, and performing an erase verification operation only on a subgroup of the cell ensemble being erased to check if the memory cells threshold voltage (Vt) has been lowered to an erase verify (EV) voltage level.
摘要翻译： 一种擦除存储器阵列中的存储单元的方法，该方法包括
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公开(公告)号：EP1685571A2
公开(公告)日：2006-08-02
申请号：EP04791844.6
申请日：2004-10-27
发明人： COHEN, Guy
CPC分类号： G11C11/5642 , G06F11/1008 , G11C16/28 , G11C16/30 , G11C16/3436 , G11C29/24 , G11C29/50 , G11C2029/0409 , G11C2029/5004 , G11C2211/5634
摘要： The present invention is a method, circuit and system for determining a reference voltage. Some embodiments of the present invention relate to a system, method and circuit for establishing a set of operating reference cells to be used in operating (e.g. reading) cells in an NVM block or array. As part of the present invention, at least a subset of cells of the NVM block or array may be read using each of two or more sets of test reference cells, where each set of test reference cells may generate or otherwise provide reference voltages at least slightly offset from each other set of test reference cells. For each set of test reference cells used to read the at least a subset of the NVM block, a read error rate may be calculated or otherwise determined. A set of test reference cells associated with a relatively low read error rate may be selected as the set of operating reference cells to be used in operating (e.g. reading) other cells, outside the subset of cells, in the NVM block or array. In a further embodiment, the selected set of test reference cells may be used to establish an operating set of reference cells having reference voltages substantially equal to those of the selected test set.
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公开(公告)号：EP1227498A3
公开(公告)日：2004-06-30
申请号：EP02250357.7
申请日：2002-01-18
发明人： Eliyahu, Ron , Maayan, Eduardo , Bloom, Ilan , Eitan, Boaz
CPC分类号： G11C16/3427 , G11C11/5671 , G11C16/0475 , G11C16/10 , G11C16/14 , G11C16/3418
摘要： A method for operating an electrically erasable programmable read only memory (EEPROM) array includes providing an array including a multiplicity of memory cells, wherein each memory cell is connected to a word line and to two bit lines, selecting one of the memory cells, and erasing a bit of the selected memory cell while applying an inhibit word line voltage to a gate of an unselected memory cell. An EEPROM array is also described, the array including a multiplicity of NROM memory cells, wherein each memory cell is connected to a word line and to two bit lines, and wherein each NROM cell is individually erasable and individually programmable without significantly disturbing unselected cells.
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10.发明公开NROM CELL WITH IMPROVED PROGRAMMING, ERASING AND CYCLING 审中-公开NROM-ZELLE MIT VERBESSERTEM PROGRAMMIEREN，LÖSCHENUND ZYKLEN
公开(公告)号：EP1082763A4
公开(公告)日：2003-01-02
申请号：EP99921112
申请日：1999-05-13
发明人： EITAN BOAZ
IPC分类号： H01L21/8247 , G11C11/56 , G11C16/04 , H01L21/265 , H01L21/336 , H01L21/8246 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , G11C11/5671 , G11C16/0475 , H01L21/26586 , H01L27/115 , H01L29/66825 , H01L29/66833 , H01L29/7923
摘要： A nitride programmable read only memory (NROM) cell with a pocket implant (120) self-aligned to at least one bit line junction (102, 104). Alternatively, the bit line junction(s) (102, 104) can have a thin area of effective programming and erasing located nearby. Further alternatively, the channel (100) can have a threshold voltage level implant which has a low voltage level in a central area of the channel (100) and which has a peak of high voltage level near at least one of the bit line junctions (102, 104). With one pocket implant, the NROM cell stores one bit. With two pocket implants, the NROM cell stores two bits.
摘要翻译： 氮化物可编程只读存储器（NROM）单元，具有与至少一个位线结自对准的凹穴注入。 或者，位线结可以具有位于附近的有效编程和擦除的薄区域。 另外，通道可以具有阈值电压电平注入，其在通道的中心区域具有低电压电平，并且在位线结中的至少一个附近具有高电压电平的峰值。 使用一个口袋植入物，NROM单元存储一位。 使用两个口袋种植体，NROM单元格存储两个位。
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