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公开(公告)号：EP3792960A2
公开(公告)日：2021-03-17
申请号：EP20204856.7
申请日：2017-04-07
发明人： Moitzi, Heinz , Drofenik, Dietmar
IPC分类号： H01L21/56 , H01L23/538 , H01L21/60 , H01L23/31 , H05K1/18 , H01L21/683
摘要： A method of manufacturing a batch of component carriers (600), wherein the method comprises providing a plurality of separate wafer structures (400), each comprising a plurality of electronic components (402), simultaneously laminating the wafer structures (400) with at least one electrically conductive layer structure (300, 404, 500) and at least one electrically insulating layer structure (300, 404, 500), and singularizing a structure resulting from the laminating into the plurality of component carriers (600), each comprising at least one of the electronic components (402), a part of the at least one electrically conductive layer structure (300, 404, 500) and a part of the at least one electrically insulating layer structure (300, 404, 500).
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公开(公告)号：EP3869923A1
公开(公告)日：2021-08-25
申请号：EP20158509.8
申请日：2020-02-20
摘要： The present invention relates to a component carrier (100) comprising a stack (101) comprising at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a component (102) embedded in the stack (101); a first thermally conductive block (103) above and thermally connected with the component (102), and a second thermally conductive block (104) below and thermally coupled with the component (102). The heat generated by the component (102) during operation is removed via at least one of the first thermally conductive block (103) and the second thermally conductive block (104).
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公开(公告)号：EP3792960A3
公开(公告)日：2021-06-02
申请号：EP20204856.7
申请日：2017-04-07
发明人： Moitzi, Heinz , Drofenik, Dietmar
IPC分类号： H01L21/56 , H01L23/538 , H01L21/60 , H01L23/31 , H05K1/18 , H01L21/683
摘要： A method of manufacturing a batch of component carriers (600), wherein the method comprises providing a plurality of separate wafer structures (400), each comprising a plurality of electronic components (402), simultaneously laminating the wafer structures (400) with at least one electrically conductive layer structure (300, 404, 500) and at least one electrically insulating layer structure (300, 404, 500), and singularizing a structure resulting from the laminating into the plurality of component carriers (600), each comprising at least one of the electronic components (402), a part of the at least one electrically conductive layer structure (300, 404, 500) and a part of the at least one electrically insulating layer structure (300, 404, 500).
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