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公开(公告)号：EP1576725A4
公开(公告)日：2008-03-26
申请号：EP03794600
申请日：2003-09-04
申请人： CIRRUS LOGIC INC
发明人： MELANSON JOHN LAURENCE , FEI XIAOFAN , GABORIAU JOHANN GUY , GREEN STEVEN , RHODE JASON P , WALBURGER ERIC , TAYLOR WILSON E JR
CPC分类号： H03F3/2175 , H03F1/52 , H03F3/2173 , H03F2200/331 , H03F2200/447
摘要： A thermal sensor at the output of a switching amplifier senses heat dissipation at the output switch. If an overheating condition is sensed, gain of the digital input signal is lowered to reduce output power of the audio output signal.
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2.发明公开METHOD AND SYSTEM OF INTEGRATING A MISMATCH NOISE SHAPER INTO THE MAIN LOOP OF A DELTA-SIGMA MODULATOR 有权方法和系统用于整合FEHLANPASSUNGSRAUSCHFORMERS在主回路的Δ-Σ调制
公开(公告)号：EP1547250A4
公开(公告)日：2006-05-17
申请号：EP03788494
申请日：2003-08-14
申请人： CIRRUS LOGIC INC
CPC分类号： H03M3/338 , H03M1/0668 , H03M3/424 , H03M3/458 , H03M3/50 , H03M7/3026
摘要： A method and system for integrating a mismatch noise shaper (108) into the main loop of a delta-sigma modulator (100) are disclosed. The output of the mismatch noise shaper (108) is fed back to the summer (102) as a feedback signal that is responsive to the mismatch noise shaper (108). At appropriate times, the mismatch noise shaper (108) selectively overrides the quantizer so that the output of the noise shaper differs from an output of the quantizer. The overriding feature distinguishes the present invention from a DEM, as the output of a DEM is only a re-ordering of the same number of elements as its input. The mismatch noise shaper (108) selectively overrides the quantizer when the output of the quantizer has prevented the mismatch noise shaper (108) to control selection of elements at the output of the mismatch noise shaper (108) for a pre-determined time period.
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3.发明公开DATA CONVERTERS WITH DIGITALLY FILTERED PULSE WIDTH MODULATION OUTPUT STAGES AND METHODS AND SYSTEMS USING THE SAME 审中-公开具有数字滤波的脉冲宽度调制输出电平和方法和系统的数据转换器，
公开(公告)号：EP1568139A4
公开(公告)日：2009-05-27
申请号：EP03768653
申请日：2003-11-04
申请人： CIRRUS LOGIC INC
摘要： A digital to analog (DAC, ADC) converter including a noise shaping modulator for modulating an input digital data stream, a plurality of output elements for generating a plurality of intermediate data streams from a modulated output stream from the modulator, and an output summer for summing the intermediate data streams to generate an output analog stream. The noise shaping modulator balances an edge transition rate of the output elements, such that the edge transition rate of two selected elements is approximately equal.
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4.发明公开NOISE SHAPERS WITH SHARED AND INDEPENDENT FILTERS AND MULTIPLE QUANTIZERS AND DATA CONVERTERS 审中-公开一起使用，独立滤波器和几种量化和数据转换器噪声整形
公开(公告)号：EP1543623A4
公开(公告)日：2006-01-18
申请号：EP03766930
申请日：2003-07-29
申请人： CIRRUS LOGIC INC
CPC分类号： H03M7/3006 , H03M3/35 , H03M3/42 , H03M3/452 , H03M7/302 , H03M7/3037
摘要： A noise shaper including first and second quantizers and first and second feedback paths each providing feedback from a corresponding quantizer output. A loop filter system implements a plurality of transfer functions including a first non-zero transfer function between the first feedback path and an input of the first quantizer, a second non-zero transfer function between the first feedback path and an input of the second quantizer, a third non-zero transfer function between the second feedback path and the input of the first quantizer and a fourth non-zero transfer between the second feedback path and the input the second quantizer.
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5.发明公开POWER SUPPLY BASED AUDIO COMPRESSION FOR DIGITAL AUDIO AMPLIFIER 审中-公开ON基于功率的音频压缩由于F R甲DIGITALAUDIOVERSTûRKER
公开(公告)号：EP1543612A4
公开(公告)日：2007-06-06
申请号：EP03756794
申请日：2003-09-04
申请人： CIRRUS LOGIC INC
CPC分类号： H03G7/007 , H03F3/181 , H03F3/217 , H03F2200/03 , H03F2200/331 , H03F2200/351 , H03G3/3089
摘要： A gain control (12) at the input monitors an input signal (DIGITAL INPUT) and a supply voltage (V+), which drives an output. The gain control (12) adjusts the gain to compress the input signal when the supply voltage decreases in magnitude and/or the input is of such magnitude to cause the supply voltage to decrease.
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6.发明公开SAMPLE AND HOLD CIRCUITS AND METHODS WITH OFFSET ERROR CORRECTION AND SYSTEMS USING THE SAME 有权采样保持电路和方法的研究偏移误差修正和系统
公开(公告)号：EP1614149A4
公开(公告)日：2006-04-26
申请号：EP04759862
申请日：2004-04-15
申请人： CIRRUS LOGIC INC
CPC分类号： G11C27/024
摘要： A sample and hold circuit including a sampling capacitor for storing a sample of an input signal, an output stage for outputting the sample stored on the sampling capacitor; and input circuitry for sampling the input signal and storing the sample on the sampling capacitor. The input circuitry includes an autozeroing input buffer which selectively samples the input signal during a first operating phase and holds a sample of the input signal during a second operating phase. The autozeroing input buffer cancels any offset error. The input circuitry also includes switching circuitry for selectively coupling the sampling capacitor with an input of the sample and hold circuitry during the second operating phase and to an output of the autozeroing input buffer during the first operating phase.
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公开(公告)号：EP1391039A4
公开(公告)日：2005-12-07
申请号：EP02726798
申请日：2002-04-25
申请人： CIRRUS LOGIC INC
CPC分类号： H03M1/0665 , H03M1/74 , H03M3/464
摘要： A method and system of operating dynamic element matching ("DEM") system with two or more power supplies are disclosed. A connection system (12) of the DEM system is driven with one power supply operating at one voltage. Connection system couples to components that are to be matched and equalized in usage by ordering outputs to components and activating the components according to ordered outputs. A connection calculator (16) of the DEM system is driven with another power supply operating at another voltage different from the one voltage. Connection calculator is coupled to the connection system, and connection calculator calculates an order of usage of components. A level shifter system (14) level shifts voltage levels of signals from connection system to connection calculator, and another level shifter system (18) level shifts voltage levels of signals from connection calculator to connection system.
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8.发明公开DELTA-SIGMA MODULATION CIRCUITS AND METHODS UTILIZING MULTIPLE NOISE ATTENUATION BANDS AND DATA CONVERTERS USING THE SAME 审中-公开delta-sigma调制线路及多噪音阻尼带与数据转换器订购方法
公开(公告)号：EP1540826A4
公开(公告)日：2005-10-12
申请号：EP03728420
申请日：2003-04-16
申请人： CIRRUS LOGIC INC
CPC分类号： H03M7/3006 , H03M7/3026 , H03M7/304
摘要： A noise shaper including a filter system (501a, 50b) for generating a first set of poles and zeros characterizing noise attenuation in a signal baseband of a noise transfer function and at least one additional set of at least one pole and one zero characterizing noise attenuation in at least one additional band outside the baseband of the noise transfer function.
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9.发明公开AUDIO DATA PROCESSING SYSTEMS AND METHODS UTILIZING HIGH OVERSAMPLING RATES 审中-公开AUDIO IT系统和具有高过扫描速率程序
公开(公告)号：EP1606722A4
公开(公告)日：2009-04-22
申请号：EP04715066
申请日：2004-02-26
申请人： CIRRUS LOGIC INC
CPC分类号： G10L19/038 , G10L19/008
摘要： A method of processing digital audio data includes receiving an input stream of audio data having a first quantization and a high oversampling rate. The input stream is requantized in a first processing block at the high oversampling rate to a second quantization. The requantized stream of audio data is processed in a second processing block at the high oversampling rate and the second quantization.
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10.发明公开
公开(公告)号：EP1433256A4
公开(公告)日：2007-12-19
申请号：EP02739703
申请日：2002-06-05
申请人： CIRRUS LOGIC INC
IPC分类号： H03F3/217 , H03H11/28 , H03K17/14 , H03K17/695
CPC分类号： H03F3/2171 , H03F2200/294 , H03F2200/372 , H03K17/145
摘要： An output stage 300 includes a first output switch 201 having a current path for driving an output from a first voltage rail and a second output switch 202 having a current path for selectively driving the output from a second voltage rail. A first reference switch 301 is scaled with respects to first output switch 201 and has a current path coupled to the first voltage rail. A second reference switch 302 scaled with respect to second output switch 202 has a current path coupled to a current path of first reference switch 301 at a node and the second voltage rail. The logic measures an impedance mismatch between first and second reference switches 301, 302 and proportionally varies the impedance of a selected one of first and second output switches 201, 202 in response.
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