公开(公告)号：EP1523229B1

公开(公告)日：2007-10-24

申请号：EP04025133.2

申请日：1999-06-30

Applicant: FormFactor, Inc.

Inventor： Pedersen, David V. ,  Eldridge, Benjamin N. ,  Khandros, Igor Y.

IPC: H05K3/32 ,  G01R1/04

CPC classification number: G01R1/0466 ,  G01R1/0408 ,  G01R1/0433 ,  G01R31/01 ,  G01R31/2863 ,  G01R31/2867 ,  G01R31/2893 ,  H01L21/67294 ,  H01L23/04 ,  H01L23/13 ,  H01L23/32 ,  H01L23/5385 ,  H01L24/72 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2224/73251 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/16152 ,  H05K3/325 ,  H05K2201/09472 ,  H01L2924/00 ,  H01L2224/72

Abstract: Products and assemblies are provided for socketably receiving elongate interconnection elements (516), such as spring contact elements, extending from electronic components (518), such as semiconductor devices. Socket substrates (504) are provided with capture pads (506) for receiving ends of elongate interconnection elements (516) extending from electronic components (518). Various capture pad configurations are disclosed. A securing device such as a housing (520) positions the electronic component securely to the socket substrate (504). Connections to external devices are provided via conductive traces (510) adjacent the surface of the socket substrate. The socket substrate (504) may be supported by a support substrate (502). In a particularly preferred embodiment the capture pads are formed directly on a primary substrate such as a printed circuit board.

公开(公告)号：EP1321978A2

公开(公告)日：2003-06-25

申请号：EP03003489.6

申请日：1997-05-15

Applicant: FORMFACTOR, INC.

Inventor： Khandros, Igor Y. ,  Pedersen, David V.

IPC: H01L21/48 ,  H01L21/60 ,  H05K1/18 ,  H05K3/34

CPC classification number: H01L23/49811 ,  G01R1/06716 ,  G01R1/06744 ,  G01R1/07342 ,  G01R3/00 ,  G01R31/287 ,  G01R31/2884 ,  G01R31/2889 ,  H01H1/0036 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/45144 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K3/20 ,  H05K3/3421 ,  H05K3/4015 ,  H01L2224/13099 ,  H01L2924/00

Abstract: Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate (106 and 108) having active electronic components (106a, 106b, 106c, 106d) such as ASICs mounted to an interconnection substrate (108) or incorporated therein, metallic spring contact element (110) effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) (102a, 102b, 102c, 102d) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements (110) may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. A significant reduction in interconnect count and consequent simplification of the interconnection substrate (108) is realized because the ASICs are capable of receiving a plurality of signals for testing the DUTs over relatively few signal lines from a host controller (116) and promulgating these signals over the relatively many interconnections between the ASICs and the DUTS.

Abstract translation: 用于执行半导体器件的晶片级老化和测试的技术包括具有有源电子部件（106a，106b，106c，106d）的测试基板（106和108），例如安装到互连基板（108）上的或并入其中的ASIC 金属弹簧接触元件（110）在待测晶片（WUT）上实现ASIC与被测试（DUT）（102a，102b，102c，102d）之间的互连之间的互连，全部处于真空中 容器，使得ASIC可以在独立于并显着低于DUT的老化温度的温度下操作。 弹簧接触元件（110）可以被安装到DUT或ASIC上，并且可以扇出来放松对ASIC和DUT的对准和互连的容限约束。 由于ASIC能够通过相对较少的来自主机控制器（116）的信号线来接收用于测试DUT的多个信号，并且将这些信号发布出去，所以实现互连数量的显着减少和互连衬底（108）的随后的简化。 ASIC和DUTS之间的相对多的互连。

公开(公告)号：EP1321978B1

公开(公告)日：2010-02-17

申请号：EP03003489.6

申请日：1997-05-15

Applicant: FormFactor, Inc.

Inventor： Khandros, Igor Y. ,  Pedersen, David V.

IPC: H01L21/48 ,  H01L21/60 ,  H05K1/18 ,  H05K3/34 ,  G01R1/073

CPC classification number: H01L23/49811 ,  G01R1/06716 ,  G01R1/06744 ,  G01R1/07342 ,  G01R3/00 ,  G01R31/287 ,  G01R31/2884 ,  G01R31/2889 ,  H01H1/0036 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/45144 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K3/20 ,  H05K3/3421 ,  H05K3/4015 ,  H01L2224/13099 ,  H01L2924/00

Abstract: Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate (106 and 108) having active electronic components (106a, 106b, 106c, 106d) such as ASICs mounted to an interconnection substrate (108) or incorporated therein, metallic spring contact element (110) effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) (102a, 102b, 102c, 102d) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements (110) may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. A significant reduction in interconnect count and consequent simplification of the interconnection substrate (108) is realized because the ASICs are capable of receiving a plurality of signals for testing the DUTs over relatively few signal lines from a host controller (116) and promulgating these signals over the relatively many interconnections between the ASICs and the DUTS.

公开(公告)号：EP1523229A3

公开(公告)日：2005-07-27

申请号：EP04025133.2

申请日：1999-06-30

Applicant: FormFactor, Inc.

Inventor： Pedersen, David V. ,  Eldridge, Benjamin N. ,  Khandros, Igor Y.

IPC: H05K3/32 ,  G01R1/04

CPC classification number: G01R1/0466 ,  G01R1/0408 ,  G01R1/0433 ,  G01R31/01 ,  G01R31/2863 ,  G01R31/2867 ,  G01R31/2893 ,  H01L21/67294 ,  H01L23/04 ,  H01L23/13 ,  H01L23/32 ,  H01L23/5385 ,  H01L24/72 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2224/73251 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/16152 ,  H05K3/325 ,  H05K2201/09472 ,  H01L2924/00 ,  H01L2224/72

Abstract: Products and assemblies are provided for socketably receiving elongate interconnection elements (516), such as spring contact elements, extending from electronic components (518), such as semiconductor devices. Socket substrates (504) are provided with capture pads (506) for receiving ends of elongate interconnection elements (516) extending from electronic components (518). Various capture pad configurations are disclosed. A securing device such as a housing (520) positions the electronic component securely to the socket substrate (504). Connections to external devices are provided via conductive traces (510) adjacent the surface of the socket substrate. The socket substrate (504) may be supported by a support substrate (502). In a particularly preferred embodiment the capture pads are formed directly on a primary substrate such as a printed circuit board.

公开(公告)号：EP1523229A2

公开(公告)日：2005-04-13

申请号：EP04025133.2

申请日：1999-06-30

Applicant: FormFactor, Inc.

Inventor： Pedersen, David V. ,  Eldridge, Benjamin N. ,  Khandros, Igor Y.

IPC: H05K3/32 ,  G01R1/04

CPC classification number: G01R1/0466 ,  G01R1/0408 ,  G01R1/0433 ,  G01R31/01 ,  G01R31/2863 ,  G01R31/2867 ,  G01R31/2893 ,  H01L21/67294 ,  H01L23/04 ,  H01L23/13 ,  H01L23/32 ,  H01L23/5385 ,  H01L24/72 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2224/73251 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/16152 ,  H05K3/325 ,  H05K2201/09472 ,  H01L2924/00 ,  H01L2224/72

Abstract: Products and assemblies are provided for socketably receiving elongate interconnection elements (516), such as spring contact elements, extending from electronic components (518), such as semiconductor devices. Socket substrates (504) are provided with capture pads (506) for receiving ends of elongate interconnection elements (516) extending from electronic components (518). Various capture pad configurations are disclosed. A securing device such as a housing (520) positions the electronic component securely to the socket substrate (504). Connections to external devices are provided via conductive traces (510) adjacent the surface of the socket substrate. The socket substrate (504) may be supported by a support substrate (502). In a particularly preferred embodiment the capture pads are formed directly on a primary substrate such as a printed circuit board.

Abstract translation: 提供产品和组件用于可插拔地接收从诸如半导体器件的电子部件（518）延伸的细长互连元件（516），例如弹簧接触元件。 插座衬底（504）设置有用于接收从电子部件（518）延伸的细长互连元件（516）的端部的捕获焊盘（506）。 公开了各种捕获垫结构。 诸如壳体（520）的固定装置将电子部件牢固地定位到插座基板（504）。 通过与插座基板的表面相邻的导电迹线（510）提供与外部设备的连接。 插座衬底（504）可以由支撑衬底（502）支撑。 在特别优选的实施例中，捕获垫直接形成在诸如印刷电路板的主要衬底上。

公开(公告)号：EP1321978A3

公开(公告)日：2004-08-25

申请号：EP03003489.6

申请日：1997-05-15

Applicant: FORMFACTOR, INC.

Inventor： Khandros, Igor Y. ,  Pedersen, David V.

IPC: H01L21/48 ,  H01L21/60 ,  H05K1/18 ,  H05K3/34 ,  G01R1/073

CPC classification number: H01L23/49811 ,  G01R1/06716 ,  G01R1/06744 ,  G01R1/07342 ,  G01R3/00 ,  G01R31/287 ,  G01R31/2884 ,  G01R31/2889 ,  H01H1/0036 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/45144 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K3/20 ,  H05K3/3421 ,  H05K3/4015 ,  H01L2224/13099 ,  H01L2924/00

Abstract: Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate (106 and 108) having active electronic components (106a, 106b, 106c, 106d) such as ASICs mounted to an interconnection substrate (108) or incorporated therein, metallic spring contact element (110) effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) (102a, 102b, 102c, 102d) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements (110) may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. A significant reduction in interconnect count and consequent simplification of the interconnection substrate (108) is realized because the ASICs are capable of receiving a plurality of signals for testing the DUTs over relatively few signal lines from a host controller (116) and promulgating these signals over the relatively many interconnections between the ASICs and the DUTS.