公开(公告)号：EP2903399A1

公开(公告)日：2015-08-05

申请号：EP12885910.5

申请日：2012-09-26

Applicant: Meiko Electronics Co., Ltd.

Inventor： SHIMIZU, Ryoichi ,  IWAMOTO, Mitsuo ,  TODA, Mitsuaki

IPC: H05K3/46 ,  H05K1/02

CPC classification number: H05K1/188 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L2221/68359 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/2741 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32245 ,  H01L2224/82039 ,  H01L2224/82132 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2924/14 ,  H05K1/0269 ,  H05K1/0284 ,  H05K1/09 ,  H05K1/115 ,  H05K3/305 ,  H05K3/4007 ,  H05K2201/0335 ,  H05K2201/09154 ,  H05K2201/0939 ,  H05K2201/09472 ,  H05K2201/09918 ,  H05K2203/0353 ,  H05K2203/0361 ,  H05K2203/063 ,  Y02P70/613 ,  Y10T29/49131

Abstract: In the present invention, in a mark forming step in a manufacturing method for a component incorporated substrate in which an electronic component (14) is positioned with reference to a mark (12) formed in a copper layer (4), when an imaginary line extending from a search center (74), which is a center of a search range (72) of a sensor, to an edge side (78) of the search range (72) is represented as a search reference line (80) and an imaginary line extending, in a state in which a mark center (76), which is the center of the mark (12), is matched with the search center (74), from the mark center (76) in the same direction as the search reference line (80) and to an outer ridgeline (25) of the mark (12) is represented as a mark reference line (82), the mark (12) is formed in a shape in which the outer ridgeline (25) of the mark (12) is present in a position where a length of the mark reference line (82) is in a range of 30% or more of the search reference line (80).

Abstract translation: 在本发明中，在制造方法的标记形成工序的元件基板并入在其中的铜层（4）当虚线形成电子部件（14）被定位成与参考标记（12） 从搜索中心（74），所有这些是一个传感器的搜索范围（72）的中心，在搜索范围的边缘侧（78）延伸（72）被表示为搜索基准线（80）和在 假想延长线，在其中的状态下的标记中心（76），所有这些是标记的中心（12）与搜索中心（74）匹配时，来自在相同的方向上的中心标记（76） 搜索基准线（80）和在所述标记（12）的外脊线（25）被表示为标记参考线（82），标记（12）的形状被形成，其中所述外棱线（25）的 标记（12）是存在于一个位置，其中标记参考线（82）的长度的范围内的搜索基准线（80）的30％或更多。

公开(公告)号：EP2897447A1

公开(公告)日：2015-07-22

申请号：EP12884630.0

申请日：2012-09-11

Applicant: Meiko Electronics Co., Ltd.

Inventor： YAMAKI, Akira ,  KIKUCHI, Tatsuya ,  TODA, Mitsuaki

IPC: H05K3/46 ,  H05K1/02 ,  H05K3/34

CPC classification number: H05K3/0008 ,  C25D7/0607 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L2221/68359 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/2741 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32245 ,  H01L2224/82039 ,  H01L2224/82132 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0269 ,  H05K1/09 ,  H05K1/185 ,  H05K1/188 ,  H05K3/305 ,  H05K3/4007 ,  H05K3/403 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4655 ,  H05K3/4658 ,  H05K3/4661 ,  H05K3/4682 ,  H05K2201/0209 ,  H05K2201/0293 ,  H05K2201/09063 ,  H05K2201/09472 ,  H05K2201/09918 ,  H05K2203/0353 ,  H05K2203/0361 ,  H05K2203/063 ,  H01L2924/00

Abstract: A manufacturing method for a component incorporated substrate according to the present invention includes positioning an electronic component (14) with reference to a mark (12) formed on a copper layer (4), the mark (12) consisting of a material less easily etched than copper by a copper etching agent used for etching of copper, after mounting the electronic component (14) on the copper layer (4) with an adhesive layer (18) interposed therebetween, embedding the electronic component (14) and the mark (12) in an insulating substrate (34), thereafter, etching and removing a part of the copper layer (4) to form a window (W1) for exposing the mark (12), forming an LVH (46) reaching a terminal (20) of the electronic component (14) with reference to the exposed mark (12), electrically connecting the terminal (20) and the copper layer (4) via a conduction via (47) formed by applying copper plating to the LVH (46), and, thereafter, forming the copper layer (4) into a wiring pattern (50).

Abstract translation: 为雅鼎在本发明的成分掺入底物的制造方法包括与基准电子元件（14）的定位，以形成的铜层（4），标记（12）上的标记（12）由较不容易被蚀刻的材料 比铜蚀刻剂的铜用于铜的腐蚀，在安装铜层（4）与所述电子部件（14）在之间夹有粘合剂层（18），嵌入所述电子部件（14）和所述标记之后（12 ）在绝缘基板（34），之后，蚀刻并除去铜层（4），以形成用于暴露标记（12）的窗口（W1）的一部分，在LVH形成（46）到达一个终端（20） 参照暴露标记（12）的电子元件（14）电通孔（47）通过施加镀铜到LVH FORMED经由传导连接终端（20）和铜层（4）的（46） 并且，此后，形成铜层（4）为布线图案（50）。

公开(公告)号：EP1890872A4

公开(公告)日：2015-04-22

申请号：EP06760562

申请日：2006-05-31

Applicant: TEXAS INSTRUMENTS INC

Inventor： EDWARDS DARVIN R ,  CHIU TZ-CHENG ,  ZENG KEJUN

IPC: B32B15/08 ,  B32B15/20 ,  H01L23/532

CPC classification number: H05K3/3436 ,  H01L21/4846 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/09 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2203/1105 ,  Y02P70/613 ,  Y10T428/12715 ,  Y10T428/1291 ,  Y10T428/24917 ,  H01L2924/00

Abstract: A metal interconnect structure ( 100 ) comprising a bond pad ( 101 ), which has copper with at least 70 volume percent composed of crystal grains expanding more than 1 mum in their main direction, and 30 or less volume percent composed of crystal grains, which expand less than 1 mum in their main crystal direction. A body ( 102 ) of tin alloy is in contact with the bond pad.

公开(公告)号：EP2290590B1

公开(公告)日：2015-03-11

申请号：EP10008397.1

申请日：2010-08-12

Applicant: Giesecke & Devrient GmbH

Inventor： Olbrich, Magnus

IPC: G06K19/077 ,  H01L23/13 ,  H01L23/498 ,  H01L23/52 ,  H05K1/18 ,  H05K3/30 ,  H05K3/32 ,  H05K3/40

CPC classification number: G06K19/07745 ,  G06K19/07749 ,  G06K19/0775 ,  H01L23/13 ,  H01L23/49855 ,  H01L2924/0002 ,  H05K1/183 ,  H05K3/305 ,  H05K3/326 ,  H05K3/4007 ,  H05K2201/0314 ,  H05K2201/0367 ,  H05K2201/09472 ,  H05K2201/0969 ,  H05K2201/10727 ,  H01L2924/00

公开(公告)号：EP2378547A4

公开(公告)日：2013-12-04

申请号：EP10735804

申请日：2010-01-26

Applicant: PANASONIC CORP

Inventor： YOSHIOKA SHINGO ,  FUJIWARA HIROAKI

IPC: H01L21/60 ,  G11B5/48 ,  H01L21/98 ,  H01L23/48 ,  H01L25/065

CPC classification number: H05K1/11 ,  G11B5/486 ,  H01L21/565 ,  H01L22/12 ,  H01L23/3121 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/82009 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82931 ,  H01L2224/82947 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/111 ,  H05K1/117 ,  H05K1/181 ,  H05K3/184 ,  H05K2201/0376 ,  H05K2201/09472 ,  Y02P70/611 ,  Y10T428/1171 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: One aspect of the present invention is a method of mounting a semiconductor chip having: a step of forming a resin coating 3 on a surface of a path connecting a bonding pad 2a on a surface of a semiconductor chip 2 and an electrode pad 1a formed on a surface of an insulating base material 1; a step of forming, by laser beam machining, a wiring gutter 4 having a depth that is equal to or greater than a thickness of the resin coating 3 along the path for connecting the bonding pad 2a and the electrode pad 1 a; a step of depositing a plating catalyst 5 on a surface of the wiring gutter 4; a step of removing the resin coating 3; and a step of forming an electroless plating coating 6 only at a site where the plating catalyst 5 remains. Another aspect of the present invention is a three-dimensional structure in which a wiring is formed on a surface, wherein, on the surface of the three-dimensional structure, a recessed gutter for wiring is formed, extending between mutually intersecting adjacent faces of the three-dimensional structure, and wherein at least a part of a wiring conductor is embedded in the recessed gutter for wiring.

公开(公告)号：EP2451018A4

公开(公告)日：2013-08-21

申请号：EP10794009

申请日：2010-06-18

Applicant: YAZAKI CORP

Inventor： NOMURA SHOICHI ,  NAKAMURA GORO

IPC: H01R13/52 ,  H01R12/61

CPC classification number: H01R12/613 ,  H01R13/5208 ,  H05K3/361 ,  H05K3/363 ,  H05K2201/041 ,  H05K2201/09154 ,  H05K2201/09445 ,  H05K2201/09472 ,  H05K2201/09709 ,  H05K2203/0264 ,  Y10T29/49194

Abstract: A flexible flat cable connecting structure and a flexible flat cable connecting method are provided so that a connector can be connected by pitch conversion without complicating the structure of the connector and metal molds for forming mold parts become unnecessary. A flexible flat cable connecting structure for connecting a flexible flat cable (13) in which a plurality of rectangular conductors (11) are provided in parallel and a plurality of connector terminals arranged at an array pitch different from that of the rectangular conductors comprises an intermediate cable arranging member (17) one end of which is coupled to the connector terminals and in which a plurality of branch conductors (19) are provided in parallel which are set to have mutually different longitudinal dimensions according to the array pitch. The intermediate cable arranging member (17) is laid on the flexible flat cable (13) so that the intermediate cable arranging member (17) and the flexible flat cable (13) are in the same plane and form an angle. The other ends (21) of the branch conductors (19) of the intermediate cable arranging member (17) are connected to the respective rectangular conductors (11).

公开(公告)号：EP1895586A3

公开(公告)日：2013-04-03

申请号：EP07122502.3

申请日：1998-09-28

Applicant: IBIDEN CO., LTD.

Inventor： Asai, Motoo ,  Mori, Yoji

IPC: H01L23/498 ,  H05K1/02 ,  H05K1/11 ,  H01L23/50 ,  H05K3/34 ,  H05K3/46

CPC classification number: H01L23/50 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/114 ,  H05K1/116 ,  H05K3/3457 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The invention relates to a package board having a core board (30) on each surface of which a plurality of conductor circuits are formed with an interlaminar resin insulating layer therebetween, wherein a plurality of soldering pads (75U,75D) are formed on the IC chip mounted side surface, as well as on the other side surface to be connected to another board, so that said soldering pads (75D) on the other side surface are larger than those on said IC chip side surface of said package board, and a dummy pattern (58M) is formed between conductor circuit patterns formed on said IC chip mounted side surface of said core board.

公开(公告)号：EP2481269A1

公开(公告)日：2012-08-01

申请号：EP10768427.6

申请日：2010-09-24

Applicant: Option

Inventor： VANDEBRIL, Stijn

IPC: H05K1/00 ,  H05K1/18

CPC classification number: H05K3/3436 ,  H01L2224/16225 ,  H01L2924/19105 ,  H01L2924/19107 ,  H05K1/0203 ,  H05K1/111 ,  H05K1/112 ,  H05K3/284 ,  H05K3/3494 ,  H05K2201/09063 ,  H05K2201/09127 ,  H05K2201/09472 ,  H05K2201/0969 ,  H05K2203/1178 ,  Y02P70/611 ,  Y02P70/613

Abstract: System in package (1) comprising a substrate (4) having at least a first external layer (2) comprising a first conductive patterned layer (29) and being externally accessible for electrically connecting the system in package (1) to an external electric circuit and a second internal layer (3) comprising a second conductive patterned layer (30) and being covered by the first layer (2) and electronic devices (6) provided on the substrate (4) and electrically connected to external contact pads (7) of the first conductive patterned layer (29), the devices (6) and the first and the second conductive patterned layer (29, 30) being electrically connected such as to form an internal electric circuit provided to be electronically connected to the external electric circuit, the first (2) and the second layer (3) being adjacently positioned, the electronic devices (6) being enclosed in an over mould compound,characterised in that at least one of the devices (6) is electrically connected to at least one hidden contact pad (5) of the second conductive patterned layer (30) which is accessible after removal of a removable strip (8) of the first layer (2).

公开(公告)号：EP1816905B1

公开(公告)日：2010-10-06

申请号：EP07075316.5

申请日：1998-01-23

Applicant: IBIDEN CO., LTD.

Inventor： Takada, Masaru, c/o Ibiden Co., Ltd. ,  Tsukada, Kiyotaka, c/o Ibiden Co., Ltd. ,  Kobayashi, Hiroyuki, c/o Ibiden Co., Ltd. ,  Minoura, Hisashi, c/o Ibiden Co., Ltd. ,  Ukai, Yoshikazu, c/o Ibiden Co., Ltd. ,  Kondo, Mitsuhiro, c/o Ibiden Co., Ltd.

IPC: H05K3/46

CPC classification number: H05K3/4652 ,  H01L21/486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/116 ,  H05K1/182 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/3468 ,  H05K3/3484 ,  H05K3/385 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/041 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

公开(公告)号：EP2095473A1

公开(公告)日：2009-09-02

申请号：EP07827453.7

申请日：2007-11-29

Applicant: SanDisk IL Ltd

Inventor： SALOMON, Tavi ,  ALPERT, Yuval ,  BEN-DAVID, Shahar

IPC: H01R13/64 ,  H01R12/18 ,  G06K19/077 ,  H05K1/14

CPC classification number: G11B33/0488 ,  G06K19/07732 ,  H01L2924/19107 ,  H01R12/707 ,  H01R12/721 ,  H01R13/64 ,  H05K1/117 ,  H05K1/141 ,  H05K3/284 ,  H05K2201/09472 ,  H05K2201/09781 ,  H05K2201/10159 ,  H05K2203/1316 ,  Y10T29/49208

Abstract: A double-sided USB connector (201) may include a first PCB (40) that may provide a first set of electrical contacts (42) on its first side and solder pads on its second side. The first PCB may further include a components side, solder pads, and signal traces. The double-sided USB connector (201) may also include a second PCB (38) that may provide a second set of electrical contacts (35) on its first side and terminals (46) on its second side. Contacts selected from the second set of contacts (35) may be connected to selected terminals (46),.for example through via paths in the second PCB (38). Contacts from the first and second sets of contacts (42, 35) may selectively be connected to components on the first PCB (48) using signal traces rather than wires. The first PCB (40) may be joined to the second PCB (38) by using the terminals (46), and the two PCBs (40, 38) may be packaged using a common molded body.

Abstract translation: 双面USB连接器（201）可以包括第一PCB（40），其可以在其第一侧上提供第一组电触点（42）并且在其第二侧上提供焊盘。 第一PCB可以进一步包括组件侧，焊盘和信号迹线。 双面USB连接器（201）还可以包括第二PCB（38），其可以在其第一侧上提供第二组电触点（35）并且在其第二侧上提供端子（46）。 从第二组触点（35）选择的触点可以连接到选定的端子（46），例如通过第二PCB（38）中的通路路径。 来自第一和第二组触点（42,43）的触点可以使用信号迹线而不是导线选择性地连接到第一PCB（48）上的组件。 第一PCB（40）可以通过使用端子（46）连接到第二PCB（38），并且两个PCB（40,38）可以使用共同的模制主体来封装。