公开(公告)号：EP0381405B1

公开(公告)日：1994-11-30

申请号：EP90300881.1

申请日：1990-01-29

申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

发明人： Araki, Sunao

IPC分类号： G06F11/10 ,  G11C17/12

CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G06F11/2205 ,  G11C17/12

摘要： A semiconductor memory device includes a memory cell array (10) having a plurality of memory cells (MC) and formed by a mask ROM, the memory cell array having a data area (10a) in which data (SO1 - SO16) of n bits (n is an arbitrary number) is stored and a parity area (10b) in which a one-bit parity code (Pb) relating to the data is stored. A control circuit (13, 14) supplies the memory cell array with an address and reads out the data and the one-bit parity code designated by the address. A parity check circuit (16) determines whether or not the data read out from the memory cell array has a bit error and generates correction data (CB) indicating a determination result. A memory (17) stores defective output indicating data (S1 - S16) indicating one of the n bits of the data having the bit error. A data correction circuit (15) corrects one of the n bits of the data indicated by the defective output indicating data by the correction bit.

公开(公告)号：EP0383452B1

公开(公告)日：1996-12-11

申请号：EP90300935.5

申请日：1990-01-30

申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

发明人： Kasa, Yasushi ,  Takemae, Yoshihiro ,  Nagasawa, Masanori ,  Arayama, Yuji ,  Terui, Akira ,  Araki, Sunao

IPC分类号： G06F11/20 ,  G11C11/407 ,  G11C17/16

CPC分类号： G11C29/76 ,  G06F11/006 ,  G11C11/005 ,  G11C11/407 ,  G11C17/16 ,  G11C29/822

公开(公告)号：EP0383452A3

公开(公告)日：1992-12-23

申请号：EP90300935.5

申请日：1990-01-30

申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

发明人： Kasa, Yasushi ,  Takemae, Yoshihiro ,  Nagasawa, Masanori ,  Arayama, Yuji ,  Terui, Akira ,  Araki, Sunao

IPC分类号： G06F11/20 ,  G11C11/407 ,  G11C17/16

CPC分类号： G11C29/76 ,  G06F11/006 ,  G11C11/005 ,  G11C11/407 ,  G11C17/16 ,  G11C29/822

摘要： A semiconductor memory device comprises a first memory (16, 70, 201-208, 321, 420, 501) comprising memory cells for prestoring fixed data, a decoder (14, 15, 71, 72, 209-216, 225-228, 302, 305, 505, 506) for decoding an input address and for reading out a fixed data from the first memory based on a decoded input address, a second memory (23, 82, 235, 322, 331, 411, 502, 503) for storing a data identical to that prestored in a defective memory cell of the first memory, where the second memory comprising programmable non-volatile memory cells, a discriminating part (13, 75, 76, 96, 308, 309, 426, 522, 523, 531) including a third memory (63, 64, 73, 74, 93, 94, 95, 307, 423, 504) for storing a redundant address of each defective memory cell of the first memory for discriminating whether or not the input address coincides with the redundant address and for outputting a discrimination signal when the input address coincides with the redundant address, and a selecting part (25, 80, 305, 309, 426, 506) supplied with data read out from the first and second memories for normally outputting the data read out from the first memory and selectively outputting the data from the second memory when the discrimination signal is received from the discriminating part.

公开(公告)号：EP0383452A2

公开(公告)日：1990-08-22

申请号：EP90300935.5

申请日：1990-01-30

申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

发明人： Kasa, Yasushi ,  Takemae, Yoshihiro ,  Nagasawa, Masanori ,  Arayama, Yuji ,  Terui, Akira ,  Araki, Sunao

IPC分类号： G06F11/20 ,  G11C11/407 ,  G11C17/16

CPC分类号： G11C29/76 ,  G06F11/006 ,  G11C11/005 ,  G11C11/407 ,  G11C17/16 ,  G11C29/822

摘要： A semiconductor memory device comprises a first memory (16, 70, 201-208, 321, 420, 501) comprising memory cells for prestoring fixed data, a decoder (14, 15, 71, 72, 209-216, 225-228, 302, 305, 505, 506) for decoding an input address and for reading out a fixed data from the first memory based on a decoded input address, a second memory (23, 82, 235, 322, 331, 411, 502, 503) for storing a data identical to that prestored in a defective memory cell of the first memory, where the second memory comprising programmable non-volatile memory cells, a discriminating part (13, 75, 76, 96, 308, 309, 426, 522, 523, 531) including a third memory (63, 64, 73, 74, 93, 94, 95, 307, 423, 504) for storing a redundant address of each defective memory cell of the first memory for discriminating whether or not the input address coincides with the redundant address and for outputting a discrimination signal when the input address coincides with the redundant address, and a selecting part (25, 80, 305, 309, 426, 506) supplied with data read out from the first and second memories for normally outputting the data read out from the first memory and selectively outputting the data from the second memory when the discrimination signal is received from the discriminating part.

摘要翻译： 一种半导体存储器件包括包含用于的Presto环固定数据存储器单元的第一存储器（16，70，201-208，321，420，501），解码器（14，15，71，72，209-216，225-228， 302，305，505，506），用于输入地址的解码和用于从基于经解码的输入地址，第二存储器（23，82，235，322，331，411，502，503中的第一存储器中读出的固定数据 ），用于存储与在所述第一存储器中，有缺陷的存储单元并预先存储一个数据，其中所述第二存储器包括可编程非易失性存储器单元，判别部（13，75，76，96，308，309，426，522 ，523，531）包括用于识别存储在第一存储器中的每个有缺陷的存储单元的冗余地址的第三存储器（63，64，73，74，93，94，95，307，423，504）是否将 输入地址与所述冗余地址和用于输出铃声当输入地址与所述冗余地址，和一个选择部分（25，80，305，309重合一致的识别信号， 426，506）提供数据从所述第一存储器和第二存储器中读出用于正常地输出婷将数据从第一存储器和选择性地输出婷从第二存储器当从判别部所接收的识别信号中读出的数据。

公开(公告)号：EP0381405A1

公开(公告)日：1990-08-08

申请号：EP90300881.1

申请日：1990-01-29

申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

发明人： Araki, Sunao

IPC分类号： G06F11/10 ,  G11C17/12

CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G06F11/2205 ,  G11C17/12

摘要： A semiconductor memory device includes a memory cell array (10) having a plurality of memory cells (MC) and formed by a mask ROM, the memory cell array having a data area (10a) in which data (SO₁ - SO₁₆) of n bits (n is an arbitrary number) is stored and a parity area (10b) in which a one-bit parity code (Pb) relating to the data is stored. A control circuit (13, 14) supplies the memory cell array with an address and reads out the data and the one-bit parity code designated by the address. A parity check circuit (16) determines whether or not the data read out from the memory cell array has a bit error and generates correction data (CB) indicating a determination result. A memory (17) stores defective output indicating data (S₁ - S₁₆) indicating one of the n bits of the data having the bit error. A data correction circuit (15) corrects one of the n bits of the data indicated by the defective output indicating data by the correction bit.

摘要翻译： 半导体存储器件包括具有多个存储单元（MC）并由掩模ROM形成的存储单元阵列（10），该存储单元阵列具有数据区（10a），其中n位的数据（SO1-SO16） （n为任意数），存储与该数据有关的1位奇偶校验码（Pb）的奇偶校验区域（10b）。 控制电路（13,14）向存储单元阵列提供地址，并读出由地址指定的数据和一位奇偶校验码。 奇偶校验电路（16）确定从存储单元阵列读出的数据是否具有位错误，并产生指示确定结果的校正数据（CB）。 存储器（17）存储指示具有位错误的数据的n位之一的有缺陷的输出指示数据（S1-S16）。 数据校正电路（15）通过校正位来校正由缺陷输出指示数据指示的数据的n位之一。