公开(公告)号：EP0383452B1

公开(公告)日：1996-12-11

申请号：EP90300935.5

申请日：1990-01-30

申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

发明人： Kasa, Yasushi ,  Takemae, Yoshihiro ,  Nagasawa, Masanori ,  Arayama, Yuji ,  Terui, Akira ,  Araki, Sunao

IPC分类号： G06F11/20 ,  G11C11/407 ,  G11C17/16

CPC分类号： G11C29/76 ,  G06F11/006 ,  G11C11/005 ,  G11C11/407 ,  G11C17/16 ,  G11C29/822

公开(公告)号：EP0383452A3

公开(公告)日：1992-12-23

申请号：EP90300935.5

申请日：1990-01-30

申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

发明人： Kasa, Yasushi ,  Takemae, Yoshihiro ,  Nagasawa, Masanori ,  Arayama, Yuji ,  Terui, Akira ,  Araki, Sunao

IPC分类号： G06F11/20 ,  G11C11/407 ,  G11C17/16

CPC分类号： G11C29/76 ,  G06F11/006 ,  G11C11/005 ,  G11C11/407 ,  G11C17/16 ,  G11C29/822

摘要： A semiconductor memory device comprises a first memory (16, 70, 201-208, 321, 420, 501) comprising memory cells for prestoring fixed data, a decoder (14, 15, 71, 72, 209-216, 225-228, 302, 305, 505, 506) for decoding an input address and for reading out a fixed data from the first memory based on a decoded input address, a second memory (23, 82, 235, 322, 331, 411, 502, 503) for storing a data identical to that prestored in a defective memory cell of the first memory, where the second memory comprising programmable non-volatile memory cells, a discriminating part (13, 75, 76, 96, 308, 309, 426, 522, 523, 531) including a third memory (63, 64, 73, 74, 93, 94, 95, 307, 423, 504) for storing a redundant address of each defective memory cell of the first memory for discriminating whether or not the input address coincides with the redundant address and for outputting a discrimination signal when the input address coincides with the redundant address, and a selecting part (25, 80, 305, 309, 426, 506) supplied with data read out from the first and second memories for normally outputting the data read out from the first memory and selectively outputting the data from the second memory when the discrimination signal is received from the discriminating part.

公开(公告)号：EP0383452A2

公开(公告)日：1990-08-22

申请号：EP90300935.5

申请日：1990-01-30

申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

发明人： Kasa, Yasushi ,  Takemae, Yoshihiro ,  Nagasawa, Masanori ,  Arayama, Yuji ,  Terui, Akira ,  Araki, Sunao

IPC分类号： G06F11/20 ,  G11C11/407 ,  G11C17/16

CPC分类号： G11C29/76 ,  G06F11/006 ,  G11C11/005 ,  G11C11/407 ,  G11C17/16 ,  G11C29/822

摘要： A semiconductor memory device comprises a first memory (16, 70, 201-208, 321, 420, 501) comprising memory cells for prestoring fixed data, a decoder (14, 15, 71, 72, 209-216, 225-228, 302, 305, 505, 506) for decoding an input address and for reading out a fixed data from the first memory based on a decoded input address, a second memory (23, 82, 235, 322, 331, 411, 502, 503) for storing a data identical to that prestored in a defective memory cell of the first memory, where the second memory comprising programmable non-volatile memory cells, a discriminating part (13, 75, 76, 96, 308, 309, 426, 522, 523, 531) including a third memory (63, 64, 73, 74, 93, 94, 95, 307, 423, 504) for storing a redundant address of each defective memory cell of the first memory for discriminating whether or not the input address coincides with the redundant address and for outputting a discrimination signal when the input address coincides with the redundant address, and a selecting part (25, 80, 305, 309, 426, 506) supplied with data read out from the first and second memories for normally outputting the data read out from the first memory and selectively outputting the data from the second memory when the discrimination signal is received from the discriminating part.

摘要翻译： 一种半导体存储器件包括包含用于的Presto环固定数据存储器单元的第一存储器（16，70，201-208，321，420，501），解码器（14，15，71，72，209-216，225-228， 302，305，505，506），用于输入地址的解码和用于从基于经解码的输入地址，第二存储器（23，82，235，322，331，411，502，503中的第一存储器中读出的固定数据 ），用于存储与在所述第一存储器中，有缺陷的存储单元并预先存储一个数据，其中所述第二存储器包括可编程非易失性存储器单元，判别部（13，75，76，96，308，309，426，522 ，523，531）包括用于识别存储在第一存储器中的每个有缺陷的存储单元的冗余地址的第三存储器（63，64，73，74，93，94，95，307，423，504）是否将 输入地址与所述冗余地址和用于输出铃声当输入地址与所述冗余地址，和一个选择部分（25，80，305，309重合一致的识别信号， 426，506）提供数据从所述第一存储器和第二存储器中读出用于正常地输出婷将数据从第一存储器和选择性地输出婷从第二存储器当从判别部所接收的识别信号中读出的数据。

公开(公告)号：EP1118937B1

公开(公告)日：2003-10-22

申请号：EP01109451.3

申请日：1993-06-25

申请人： FUJITSU LIMITED

发明人： Akaogi, Takao ,  Takashina, Nobuaki ,  Kasa, Yasushi ,  Itano, Kiyoshi ,  Kawashima, Hiromi ,  Yamashita, Minoru ,  Kawamura, Shouichi

IPC分类号： G11C29/00

CPC分类号： G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

摘要： A semiconductor memory device having electrically erasable nonvolatile memory cells to and from which data is automatically written and erased according to an internal algorithm incorporated in said semiconductor memory device. The allowable value of write or erase operations is determined according to the internal algorithm, which is variable. Thus, a device embodying the present invention can carry out a delivery test with "n" rewrite operations at the most, and taking into account deterioration due to an increase in the number of rewrite operations, can guarantee the maximum number of rewrite operations N (N>n) possible by a user.

公开(公告)号：EP1158535A3

公开(公告)日：2002-08-14

申请号：EP01109455.4

申请日：1993-06-25

申请人： FUJITSU LIMITED

发明人： Akaogi, Takao ,  Takashina, Nobuaki ,  Kasa, Yasushi ,  Itano, Kiyoshi ,  Kawashima, Hiromi ,  Yamashita, Minoru ,  Kawamura, Shouichi

IPC分类号： G11C16/34

CPC分类号： G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

摘要： A semiconductor memory device having a plurality of word lines (WLs), a plurality of bit lines (BLs), and a memory cell array including a plurality of memory cells (MCs) each formed of a MIS transistor disposed at an intersection of a word line with a bit line. The threshold voltage of each MIS transistor is externally electrically controllable according to charges to be injected to a floating gate thereof, and the floating gates of the MIS transistors are arranged to be simultaneously discharged to collectively erase the memory cells. The invention provides means for saving overerased memory cells of the semiconductor memory device, detecting memory cells that have been overerased by the collective erasing, and writing data to the overerased memory cells, thereby saving them.

公开(公告)号：EP0935256B1

公开(公告)日：2002-05-08

申请号：EP99105448.7

申请日：1994-02-08

申请人： FUJITSU LIMITED

发明人： Kumakura, Sinsuke ,  Yamazaki, Hirokazu ,  Watanabe, Hisayoshi ,  Kasa, Yasushi

IPC分类号： G11C29/00 ,  H01L21/02

CPC分类号： G11C29/021 ,  G11C5/14 ,  G11C5/143 ,  G11C7/062 ,  G11C16/04 ,  G11C29/02 ,  G11C29/24 ,  G11C29/44 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50016 ,  G11C2029/5006

摘要： An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory comprises word lines WLi and bit lines BLi, a memory cell matrix 17 consisting of nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3,..., whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.

公开(公告)号：EP1158532A2

公开(公告)日：2001-11-28

申请号：EP01109453.9

申请日：1993-06-25

申请人： FUJITSU LIMITED

发明人： Akaogi, Takao ,  Takashina, Nobuaki ,  Kasa, Yasushi ,  Itano, Kiyoshi ,  Kawashima, Hiromi ,  Yamashita, Minoru ,  Kawamura, Shouichi

IPC分类号： G11C16/08 ,  G11C8/00

CPC分类号： G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

摘要： A semiconductor memory device having a plurality of word lines (WLs), a plurality of bit lines (BLs), and memory cells (MCs) disposed at intersections of the word lines and bit lines. A decoder circuit (901; 912, 914) selects one memory cell according to an address signal in a normal decoding function, and carries out a full selection operation or a nonselection operation of the word lines or bit lines in a test function. The decoder circuit comprises an output row or a decoding row connected to a first power source (904) and a second power source (905), the first power source supplying a high voltage (Vcc), and the second power source supplying a reference voltage (Vss) or the high voltage in response to a control signal (AH, AL).

摘要翻译： 一种半导体存储器件，具有设置在字线和位线的交叉处的多个字线（WL），多个位线（BL）和存储单元（MC）。 解码器电路（901; 912,914）根据正常解码功能中的地址信号选择一个存储器单元，并且在测试功能中执行字线或位线的完全选择操作或非选择操作。 解码器电路包括连接到第一电源（904）和第二电源（905）的输出行或解码行，第一电源提供高电压（Vcc），第二电源提供参考电压 （Vss）或响应于控制信号（AH，AL）的高电压。

公开(公告)号：EP0961289A2

公开(公告)日：1999-12-01

申请号：EP99115179.6

申请日：1992-12-09

申请人： FUJITSU LIMITED

发明人： Akaogi, Takao ,  Kawashima, Hiromi ,  Takeguchi, Tetsuji ,  Hagiwara, Ryoji ,  Kasa, Yasushi ,  Itano, Kiyoshi ,  Kawamura, Shouichi ,  Ogawa, Yasushige

IPC分类号： G11C16/06

CPC分类号： G11C29/82 ,  G05F3/205 ,  G11C5/145 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  H03K3/356147 ,  H03K3/356165 ,  H03K19/018521 ,  H03K19/215

摘要： A flash memory which includes a memory cell array (271) in which a plurality of nonvolatile memory cells that can be erased electrically are set in array and decoding units (273) that decode a plurality of signals and access said memory cell array (271), further comprises: drive units (274) each of which includes a first power terminal (275) and a second power terminal (276), inputs the output of the decoding unit (273), and selectively outputs a voltage applied to the first power terminal (275) or a voltage approximate to that voltage, and a voltage applied to the second power terminal or a voltage approximate to that voltage; the drive unit (274) assuming a first operation mode, in which a first voltage is applied to the first power terminal (275) and a second voltage that is lower than the first voltage is applied to the second power terminal (276), and a second operation mode, in which a third voltage is applied to the first power terminal (275) and a fourth voltage that is higher than the third voltage is applied to the second power terminal (276); and selecting an output voltage depending on whether the first or second operation mode is specified.

摘要翻译： 一种闪速存储器，其包括：存储单元阵列（271），其中可以电擦除的多个非易失性存储单元被设置在阵列中，并且解码多个信号并访问所述存储单元阵列（271）的解码单元（273） 还包括：各包括第一电源端子（275）和第二电源端子（276）的驱动单元（274），输入解码单元（273）的输出，并且选择性地输出施加到第一电源 端子（275）或接近该电压的电压以及施加到第二电源端子的电压或接近该电压的电压; 驱动单元（274）呈现第一操作模式，其中向第一电源端子（275）施加第一电压并且向第二电源端子（276）施加低于第一电压的第二电压，以及以及 第二操作模式，其中向所述第一电源端子（275）施加第三电压，并且向所述第二电源端子（276）施加高于所述第三电压的第四电压; 并根据是否指定第一或第二操作模式来选择输出电压。

公开(公告)号：EP0262995B1

公开(公告)日：1996-03-27

申请号：EP87401833.6

申请日：1987-08-06

申请人： FUJITSU LIMITED

发明人： Kasa, Yasushi

IPC分类号： H03K5/153 ,  G11C8/00

CPC分类号： G11C8/18 ,  H03K5/1534

公开(公告)号：EP0423495A3

公开(公告)日：1992-10-21

申请号：EP90117849.1

申请日：1990-09-17

申请人： FUJITSU LIMITED

发明人： Kasa, Yasushi ,  Arayama, Yuji ,  Hirayama, Seiji

IPC分类号： G06F11/20

CPC分类号： G11C29/787 ,  G11C29/838

摘要： This invention configures a semiconductor memory device in the following manner. The semiconductor contains a first memory part and more than one redundant circuit that is used when the first memory part is faulty, and each redundant circuit memorizes in its status memory part whether a second memory part which becomes a spare cell is in a not-in-use status, in an in-use status or in an out-of-use status, which means that a failure exists in the second memory part. If a second memory part is in the out-of-use status, its access is prohibited, and the other second memory part without a failure is accessed. With this configuration, when a spare cell is confirmed to have a failure after the spare cell is programmed, the spare cell is put in the out-of-use status, thereby preventing the spare cell from being accessed. Consequently, the yield of the semiconductor device is increased.