公开(公告)号：EP1485778A2

公开(公告)日：2004-12-15

申请号：EP03745107.7

申请日：2003-03-14

申请人： Freescale Semiconductor Inc.

发明人： MOYER, William, C. ,  FITZSIMMONS, Michael, D.

IPC分类号： G06F1/00

CPC分类号： G01R31/31719

摘要： The invention relates to an integrated circuit (IC), and more particularly to security to protect an IC (10) against unauthorized accesses. In one embodiment, an identifier is provided external to IC 10. A corresponding input IC security key (52) is then provided to IC 10 and compared to a stored IC security key (30). If the input IC security key (52) and the stored IC security key (30) do not match, access to protected functional circuitry (12) is prohibited. The present invention may use any debug interface, including standard debug interfaces using the JTAG 1149.1 interface defined by the IEEE.

公开(公告)号：EP1483648A1

公开(公告)日：2004-12-08

申请号：EP03744238.1

申请日：2003-03-05

申请人： Freescale Semiconductor, Inc.

发明人： MOYER, William, C. ,  FITZSIMMONS, Michael, D.

IPC分类号： G06F1/00

CPC分类号： G06F21/85

摘要： One embodiment of the present invention provides a flexible peripheral access protection mechanism within a data processing system (10) in order to obtain a more secure operating environment. For example, the data processing system may include a combination of secure (12) and unsecure bus masters (14, 15) needing to access shared peripherals (22, 24). One embodiment allows for the dynamic update by a secure bus master (12) of access permissions corresponding to each unsecure bus master for each peripheral. A secure bus master is therefore able to establish which unsecure bus masters have permission to access which peripheral in order to protect the data processing system from corruption due to errant or hostile software running on unsecure bus masters. Through the use of a bus master identifier (36), access to the requested peripheral is either allowed or denied based on the permissions established by the secure bus master.

公开(公告)号：EP1499906B1

公开(公告)日：2006-01-04

申请号：EP03721656.1

申请日：2003-04-14

申请人： Freescale Semiconductor, Inc.

发明人： TKACIK, Thomas ,  SPITTAL, John, E., Jr. ,  LUTZ, Jonathan ,  CASE, Lawrence ,  HARDY, Douglas ,  REDMAN, Mark ,  SCHMIDT, Gregory ,  TUGENBERG, Steven ,  FITZSIMMONS, Michael, D. ,  CARDER, Darrell, L.

IPC分类号： G01R31/3185 ,  G06F1/00

CPC分类号： G06F21/75 ,  G01R31/31719 ,  G01R31/318516 ,  G01R31/318533 ,  G01R31/318544

摘要： A processor, scan controller, and method for protecting sensitive information from electronic hacking is disclosed. To maintain the security of the sensitive data present in a processor, the scan controller denies access to the scan chain until data is cleared from scan-observable portions of the processor, then clears the scan chain again prior to exiting test mode and resuming normal operation. Clearing or otherwise modifying data stored in the scan-observable portions of a processor when transitioning to and/or from a test mode will prevent unauthorized personnel from simply shifting secure data out of the scan chain, and from pre-loading data into the scan chain prior to normal operation in an attempt to set sensitive state information.

公开(公告)号：EP1499906A1

公开(公告)日：2005-01-26

申请号：EP03721656.1

申请日：2003-04-14

申请人： Freescale Semiconductor, Inc.

发明人： TKACIK, Thomas ,  SPITTAL, John, E., Jr. ,  LUTZ, Jonathan ,  CASE, Lawrence ,  HARDY, Douglas ,  REDMAN, Mark ,  SCHMIDT, Gregory ,  TUGEBNERG, Steven ,  FITZSIMMONS, Michael, D. ,  CARDER, Darrell, L.

IPC分类号： G01R31/3185 ,  G06F1/00

CPC分类号： G06F21/75 ,  G01R31/31719 ,  G01R31/318516 ,  G01R31/318533 ,  G01R31/318544

摘要： A processor, scan controller, and method for protecting sensitive information from electronic hacking is disclosed. To maintain the security of the sensitive data present in a processor, the scan controller denies access to the scan chain until data is cleared from scan-observable portions of the processor, then clears the scan chain again prior to exiting test mode and resuming normal operation. Clearing or otherwise modifying data stored in the scan-observable portions of a processor when transitioning to and/or from a test mode will prevent unauthorized personnel from simply shifting secure data out of the scan chain, and from pre-loading data into the scan chain prior to normal operation in an attempt to set sensitive state information.

公开(公告)号：EP1483652A2

公开(公告)日：2004-12-08

申请号：EP03714002.7

申请日：2003-03-05

申请人： Freescale Semiconductor, Inc.

发明人： MOYER, William, C. ,  MILLAR, Brian, M. ,  FITZSIMMONS, Michael, D.

IPC分类号： G06F1/32

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  Y02D10/128 ,  Y02D50/20

摘要： Systems and methods are discussed to identify a recoverable state in a low power device. A low power device having an arbiter to grant system bus access to a plurality of bus masters is set to initiate a low power mode of operation. A low power controller within the low power device provides a request to the bus arbiter to initiate a low power mode. The bus arbiter stops granting bus requests to the bus masters and identifies when the system bus has processed all current bus accesses. When the system bus is idle, the bus arbiter returns a bus grant signal to the low power controller. Clocks associated with the bus masters are disabled to suspend the bus arbiters and allow less power to be consumed by the low power device.