公开(公告)号：EP1483789B1

公开(公告)日：2016-11-16

申请号：EP03714137.1

申请日：2003-03-12

Applicant: Freescale Semiconductor Inc. (A Delaware Corp)

Inventor： DOWNEY, Susan, H. ,  MILLER, James, W. ,  HALL, Geoffrey, B.

IPC: H01L21/60 ,  H01L23/485

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06135 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/01004

公开(公告)号：EP1483789A2

公开(公告)日：2004-12-08

申请号：EP03714137.1

申请日：2003-03-12

Applicant: Freescale Semiconductor Inc. (A Delaware Corp)

Inventor： DOWNEY, Susan, H. ,  MILLER, James, W. ,  HALL, Geoffrey, B.

IPC: H01L23/528

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06135 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/01004

Abstract: An integrated circuit (50) has a wire bond pad (53). The wire bond pad (53) is formed on a passivation layer (18) over active circuitry (26) and/or electrical interconnect layers (24) of the integrated circuit (50). The wire bond pad (53) is connected to a plurality of final metal layer portions (51, 52). The plurality of final metal layer portions (51, 52) are formed in a final interconnect layer of the interconnect layers (24). In one embodiment, the bond pad (53) is formed from aluminum and the final metal layer pads are formed from copper. The wire bond pad (53) allows routing of conductors in a final metal layer (28) directly underlying the bond pad (53), thus allowing the surface area of the semiconductor die to be reduced.

Abstract translation: 集成电路（50）具有引线接合焊盘（53）。 引线接合焊盘（53）形成在集成电路（50）的有源电路（26）和/或电互连层（24）上的钝化层（18）上。 引线接合焊盘（53）连接到多个最终的金属层部分（51,52）。 多个最终金属层部分（51,52）形成在互连层（24）的最终互连层中。 在一个实施例中，接合焊盘（53）由铝形成，并且最终的金属层焊盘由铜形成。 引线接合焊盘（53）允许在直接位于接合焊盘（53）下方的最终金属层（21）中布线导体，从而允许半导体管芯的表面积减小。