公开(公告)号：EP1483789B1

公开(公告)日：2016-11-16

申请号：EP03714137.1

申请日：2003-03-12

Applicant: Freescale Semiconductor Inc. (A Delaware Corp)

Inventor： DOWNEY, Susan, H. ,  MILLER, James, W. ,  HALL, Geoffrey, B.

IPC: H01L21/60 ,  H01L23/485

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06135 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/01004

公开(公告)号：EP1624570A1

公开(公告)日：2006-02-08

申请号：EP04103726.8

申请日：2004-08-03

Applicant: Freescale Semiconductor Inc. (A Delaware Corp)

Inventor： ZECRI, Michel ,  BERTOLINI, Luca ,  BESSE, Patrice ,  BAFLEUR, Marise ,  NOLHIER, Nicolas

IPC: H03K17/082

CPC classification number: H03K17/0822

Abstract: A semiconductor switch arrangement (300) comprising a bipolar transistor (302) and a semiconductor power switch (301) having an input node (306), an output node (304) and a control node (305) for allowing a current path to be formed between the input node (306) and the output node (307), wherein the bipolar transistor (302) is coupled between the input node (306) and the control node (305) to allow a current to flow from the input node (306) to the control node (305) upon a predetermined voltage being exceeded at the input node (306) to allow the control node (305) to cause a current to flow from the input node (306) to the output node (307).

Abstract translation: 一种包括双极晶体管（302）和具有输入节点（306）的半导体功率开关（301）的半导体开关装置（300），输出节点（304）和控制节点（305），用于允许当前路径 形成在输入节点（306）和输出节点（307）之间，其中双极晶体管（302）耦合在输入节点（306）和控制节点（305）之间，以允许电流从输入节点 306）在输入节点（306）上超过预定电压以允许控制节点（305）使电流从输入节点（306）流向输出节点（307）时，控制节点（305） 。

公开(公告)号：EP1497941A1

公开(公告)日：2005-01-19

申请号：EP03718340.7

申请日：2003-04-15

Applicant: Freescale Semiconductor Inc. (A Delaware Corp)

Inventor： THRON, Chris ,  KOIRALA, Dipesh ,  TAIPALE, Dana

IPC: H04L1/00 ,  H04L25/02

CPC classification number: H04L1/0038 ,  H04L1/0002 ,  H04L25/0262 ,  Y02D50/10

Abstract: An integrated circuit arranged and constructed to determine an upper data rate for a variable data rate signal and method thereof includes a buffer, comparator, and combiner that are operable to compare a characteristic, such as an energy statistic of a number of partial symbols constructed from the variable data rate signal to a first threshold that corresponds to the number to provide a first comparison; process the variable data rate signal at a first data rate when the first comparison is favorable; compare the characteristic to a second threshold that corresponds to the number to provide a second comparison; and combine the partial symbols to provide other partial symbols at a second data rate that is less than the first data rate when the second comparison is favorable.

公开(公告)号：EP1594253B1

公开(公告)日：2008-04-09

申请号：EP04291127.1

申请日：2004-05-03

Applicant: Freescale Semiconductor Inc. (A Delaware Corp)

Inventor： Bogavac, Davor

IPC: H04L12/12 ,  H04L12/413 ,  B60R16/02

CPC classification number: H04L12/12 ,  H04L12/4135 ,  H04L2012/40215 ,  Y02D50/40

Abstract: A method of communication comprising sending communication signals switched between dominant and recessive values at clock intervals in frames over a serial data bus (15 - 17) from at least one of a plurality of sending nodes (1 - 5, 8, 9, 12, 13) to a plurality of receiving nodes (1, 2, 4, 7 - 13). The receiving nodes have an operational state and a standby state in which the current consumption of the node is reduced compared to the operational state. The receiving nodes include wake-up trigger means (19) for triggering transition from the standby state to the operational state in response to the communication signals. The frames of the transmitted signals include an identifier field (ID St, ID Ex) during which the communication signal alternates between the dominant and recessive values in successive clock intervals with at least one significant occurrence during which the communication signal remains at one of the dominant and recessive values during at least two successive clock intervals, and the trigger means (19) is selectively responsive to the position of the occurrence within the identifier field for triggering the transition from the standby state to the operational state.

公开(公告)号：EP1483789A2

公开(公告)日：2004-12-08

申请号：EP03714137.1

申请日：2003-03-12

Applicant: Freescale Semiconductor Inc. (A Delaware Corp)

Inventor： DOWNEY, Susan, H. ,  MILLER, James, W. ,  HALL, Geoffrey, B.

IPC: H01L23/528

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06135 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/01004

Abstract: An integrated circuit (50) has a wire bond pad (53). The wire bond pad (53) is formed on a passivation layer (18) over active circuitry (26) and/or electrical interconnect layers (24) of the integrated circuit (50). The wire bond pad (53) is connected to a plurality of final metal layer portions (51, 52). The plurality of final metal layer portions (51, 52) are formed in a final interconnect layer of the interconnect layers (24). In one embodiment, the bond pad (53) is formed from aluminum and the final metal layer pads are formed from copper. The wire bond pad (53) allows routing of conductors in a final metal layer (28) directly underlying the bond pad (53), thus allowing the surface area of the semiconductor die to be reduced.

Abstract translation: 集成电路（50）具有引线接合焊盘（53）。 引线接合焊盘（53）形成在集成电路（50）的有源电路（26）和/或电互连层（24）上的钝化层（18）上。 引线接合焊盘（53）连接到多个最终的金属层部分（51,52）。 多个最终金属层部分（51,52）形成在互连层（24）的最终互连层中。 在一个实施例中，接合焊盘（53）由铝形成，并且最终的金属层焊盘由铜形成。 引线接合焊盘（53）允许在直接位于接合焊盘（53）下方的最终金属层（21）中布线导体，从而允许半导体管芯的表面积减小。

公开(公告)号：EP1594253A1

公开(公告)日：2005-11-09

申请号：EP04291127.1

申请日：2004-05-03

Applicant: Freescale Semiconductor Inc. (A Delaware Corp)

Inventor： Bogavac, Davor

IPC: H04L12/12 ,  H04L12/413 ,  B60R16/02

CPC classification number: H04L12/12 ,  H04L12/4135 ,  H04L2012/40215 ,  Y02D50/40

Abstract: A method of communication comprising sending communication signals switched between dominant and recessive values at clock intervals in frames over a serial data bus (15 - 17) from at least one of a plurality of sending nodes (1 - 5, 8, 9, 12, 13) to a plurality of receiving nodes (1, 2, 4, 7 - 13). The receiving nodes have an operational state and a standby state in which the current consumption of the node is reduced compared to the operational state. The receiving nodes include wake-up trigger means (19) for triggering transition from the standby state to the operational state in response to the communication signals. The frames of the transmitted signals include an identifier field (ID St, ID Ex) during which the communication signal alternates between the dominant and recessive values in successive clock intervals with at least one significant occurrence during which the communication signal remains at one of the dominant and recessive values during at least two successive clock intervals, and the trigger means (19) is selectively responsive to the position of the occurrence within the identifier field for triggering the transition from the standby state to the operational state.

Abstract translation: 一种通信方法，包括：从串行数据总线（15-17）中的时钟间隔以多个发送节点（1至5,8,9,12,12）中的至少一个发送在主要和隐性值之间切换的通信信号， 13）到多个接收节点（1,2,4,7-13）。 接收节点具有操作状态和待机状态，其中节点的电流消耗与操作状态相比降低。 接收节点包括用于响应于通信信号触发从待机状态转换到操作状态的唤醒触发装置（19）。 发送信号的帧包括标识符字段（ID St，IDEx），在该标识符字段期间，通信信号在连续时钟间隔中在主要和隐性值之间进行交替，具有至少一个显着的发生，其中通信信号保持在主导 以及在至少两个连续时钟间隔期间的隐性值，并且触发装置（19）有选择地响应于标识符字段内出现的位置，以触发从待机状态到操作状态的转变。

公开(公告)号：EP1480342A3

公开(公告)日：2005-01-19

申请号：EP04011998.4

申请日：2004-05-20

Applicant: Freescale Semiconductor Inc. (A Delaware Corp)

Inventor： Clement, Patrick

IPC: H03M1/00 ,  H03M3/04

CPC classification number: H03M1/002 ,  H03M1/361 ,  H03M3/32 ,  H03M3/424 ,  H03M3/45 ,  H03M3/454

Abstract: An analog to digital converter comprising a plurality of comparators arranged to periodically sample an analog signal; a calculator arranged to predict a change in signal magnitude of the analog signal between one sample of the analog signal and another sample of the analog signal based upon predetermined criteria of the analog signal; and a controller for varying an operational parameter of one or more of the comparators based upon the predicted change in the signal magnitude of the analog signal.

公开(公告)号：EP1480342A2

公开(公告)日：2004-11-24

申请号：EP04011998.4

申请日：2004-05-20

Applicant: Freescale Semiconductor Inc. (A Delaware Corp)

Inventor： Clement, Patrick

IPC: H03M1/00 ,  H03M3/04

CPC classification number: H03M1/002 ,  H03M1/361 ,  H03M3/32 ,  H03M3/424 ,  H03M3/45 ,  H03M3/454

Abstract: An analog to digital converter comprising a plurality of comparators arranged to periodically sample an analog signal; a calculator arranged to predict a change in signal magnitude of the analog signal between one sample of the analog signal and another sample of the analog signal based upon predetermined criteria of the analog signal; and a controller for varying an operational parameter of one or more of the comparators based upon the predicted change in the signal magnitude of the analog signal.

Abstract translation: 一种模数转换器，包括布置成周期性地对模拟信号进行采样的多个比较器; 计算器，其被布置为基于所述模拟信号的预定标准来预测所述模拟信号的一个样本与所述模拟信号的另一采样之间的所述模拟信号的信号幅度的变化; 以及控制器，用于基于模拟信号的信号幅度的预测变化来改变一个或多个比较器的操作参数。

公开(公告)号：EP1446717A1

公开(公告)日：2004-08-18

申请号：EP02789344.5

申请日：2002-10-30

Applicant: Freescale Semiconductor Inc. (A Delaware Corp)

Inventor： MOYER, William, C.

IPC: G06F9/38

CPC classification number: G06F9/3877

Abstract: The present invention relates generally to interfacing a processor (12) with at least one coprocessor (14, 16). One embodiment relates to a processor having a set of broadcast specifiers which it uses to selectively broadcast an operand that is being written to a register within the processor to a coprocessor communication bus. Each broadcast specifier may therefore include a broadcast indicator corresponding to each general purpose register of the processor. An alternate embodiment may also use the concept of broadcast regions (164, 166, 168, 170) where each broadcast region may have a corresponding broadcast specifier where one broadcast specifier may correspond to multiple broadcast regions. Alternatively, in one embodiment, the processor may use broadcast regions independent of the broadcast specifiers where the coprocessor is able to alter its functionality in response to the current broadcast region. In one embodiment, the processor may provide a region specifier (H REGION) via the coprocessor communication bus (30) to indicate the current broadcast region.

公开(公告)号：EP1480342B1

公开(公告)日：2009-03-18

申请号：EP04011998.4

申请日：2004-05-20

Applicant: Freescale Semiconductor Inc. (A Delaware Corp)

Inventor： Clement, Patrick

IPC: H03M1/00 ,  H03M3/04

CPC classification number: H03M1/002 ,  H03M1/361 ,  H03M3/32 ,  H03M3/424 ,  H03M3/45 ,  H03M3/454