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公开(公告)号：EP2074624B1
公开(公告)日：2010-03-03
申请号：EP07852786.8
申请日：2007-10-16
IPC分类号： G11C13/02
CPC分类号： G11C13/02 , B82Y10/00 , G06F11/1008 , G06F11/1076 , G11C11/54 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C2013/0047 , G11C2013/0057 , G11C2013/009 , G11C2213/16 , G11C2213/77 , G11C2213/81
摘要： Various embodiments of the present invention are directed to crossbar-memory systems to methods for writing information to and reading information stored in such systems. In one embodiment of the present invention, a crossbar-memory system (800) comprises a first layer of microscale signal lines (808), a second layer of microscale signal lines '(810), a first layer of nanowires (804) configured so that each first layer, nanowire overlaps each first layer microscale signal line (808), and a second layer of nanowires (806) configured so that each second layer nanowire overlaps each second layer microscale signal line (810) and overlaps each first layer nanowire (804). The crossbar-memory system includes nonlinear-tunneling resistors configured to selectively connect first layer nanowires (804) to first layer microscale signal lines (808) and to selectively connect second layer nanowires (806) to second layer microscale signal lines (810). The crossbar-memory system (800) also includes nonlinear tunneling-hysteretic resistors configured to connect each first layer nanowire to each second layer nanowire. at each crossbar intersection.
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公开(公告)号：EP2074624A2
公开(公告)日：2009-07-01
申请号：EP07852786.8
申请日：2007-10-16
IPC分类号： G11C13/02
CPC分类号： G11C13/02 , B82Y10/00 , G06F11/1008 , G06F11/1076 , G11C11/54 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C2013/0047 , G11C2013/0057 , G11C2013/009 , G11C2213/16 , G11C2213/77 , G11C2213/81
摘要： Various embodiments of the present invention are directed to crossbar-memory systems to methods for writing information to and reading information stored in such systems. In one embodiment of the present invention, a crossbar-memory system (800) comprises a first layer of microscale signal lines (808), a second layer of microscale signal lines '(810), a first layer of nanowires (804) configured so that each first layer, nanowire overlaps each first layer microscale signal line (808), and a second layer of nanowires (806) configured so that each second layer nanowire overlaps each second layer microscale signal line (810) and overlaps each first layer nanowire (804). The crossbar-memory system includes nonlinear-tunneling resistors configured to selectively connect first layer nanowires (804) to first layer microscale signal lines (808) and to selectively connect second layer nanowires (806) to second layer microscale signal lines (810). The crossbar-memory system (800) also includes nonlinear tunneling-hysteretic resistors configured to connect each first layer nanowire to each second layer nanowire. at each crossbar intersection.
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3.发明公开TUNNELING-RESISTOR-JUNCTION-BASED MICROSCALE/NANOSCALE DEMULTIPLEXER ARRAYS 有权基于隧穿 - 电阻 - 结点的微型/纳米级解复用器阵列
公开(公告)号：EP1979911A2
公开(公告)日：2008-10-15
申请号：EP07762918.6
申请日：2007-01-30
CPC分类号： G11C8/10 , G11C13/0023 , H03M13/51
摘要： Various embodiments of the present invention are directed to demultiplexers that include tunneling resistor nanowire junctions, and to nanowire addressing methods for reliably addressing nanowire signal lines in nanoscale and mixed-scale demultiplexers. In one embodimentof the present invention, an encoder-demulriplexer comprises a number of input signal lines and an encoder (1304) that generates an n-bit-constant-weight-code code-word internal address (1320, 1506, 1704) for each different input address (1318, 1702) received on the input signal lines. The encoder-demultiplexer also includes n microscale signal lines (1306-1311) on which an n-bit-constant-weight-code code word internal address is out put by the encoder and a number of encoder-demultiplexer-addressed nanowire signal lines interconnected with the n microscale signal lines (1306-1311) via tunneling resistor junctions, the encoder-demultiplexer-addressed nanowire signal lines each associated with an n-bit-constant-weight-code code-word internal adress (1320, 1506, 1704).
摘要翻译： 本发明的各种实施例涉及包括隧道电阻器纳米线结的解复用器，并且涉及用于在纳米级和混合尺度解复用器中可靠地寻址纳米线信号线的纳米线寻址方法。 在本发明的一个实施例中，编码器 - 解复用器包括多个输入信号线和编码器（1304），编码器（1304）为每个输入信号线生成n位恒定加权码字内部地址（1320,1506,1704） 在输入信号线上接收不同的输入地址（1318,1702）。 编码器 - 解复用器还包括n个微型信号线（1306-1311），编码器输出n位恒定加权码字内部地址，并且编码器 - 解复用器寻址的纳米线信号线互连 与n个微米级信号线（1306-1311）经由隧道电阻器结，编码器 - 解复用器寻址的纳米线信号线均与n位恒定加权码码字内部地址（1320,1506,1704）相关联， 。
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4.发明授权DEFECT-AND-FAILURE-TOLERANT DEMULTIPLEXER USING SERIES REPLICATION AND ERROR-CONTROL ENCODING 有权缺陷和容错信号分离器系列产品的复制和错误WATCHING编码
公开(公告)号：EP2038750B1
公开(公告)日：2016-05-11
申请号：EP07796813.9
申请日：2007-07-11
IPC分类号： G06F11/10 , H03K19/177
CPC分类号： H03K19/007 , G06F11/1076 , H03K19/00315
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5.发明授权TUNNELING-RESISTOR-JUNCTION-BASED MICROSCALE/NANOSCALE DEMULTIPLEXER ARRAYS 有权基于TUNNELRESISTORVERBINDUNGEN MIKROSKALA- /纳米尺度DEMULTIRPLEXER ARRAYS
公开(公告)号：EP1979911B1
公开(公告)日：2011-08-03
申请号：EP07762918.6
申请日：2007-01-30
CPC分类号： G11C8/10 , G11C13/0023 , H03M13/51
摘要： Various embodiments of the present invention are directed to demultiplexers that include tunneling resistor nanowire junctions, and to nanowire addressing methods for reliably addressing nanowire signal lines in nanoscale and mixed-scale demultiplexers. In one embodimentof the present invention, an encoder-demulriplexer comprises a number of input signal lines and an encoder (1304) that generates an n-bit-constant-weight-code code-word internal address (1320, 1506, 1704) for each different input address (1318, 1702) received on the input signal lines. The encoder-demultiplexer also includes n microscale signal lines (1306-1311) on which an n-bit-constant-weight-code code word internal address is out put by the encoder and a number of encoder-demultiplexer-addressed nanowire signal lines interconnected with the n microscale signal lines (1306-1311) via tunneling resistor junctions, the encoder-demultiplexer-addressed nanowire signal lines each associated with an n-bit-constant-weight-code code-word internal adress (1320, 1506, 1704).
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公开(公告)号：EP2946385A1
公开(公告)日：2015-11-25
申请号：EP13871450.6
申请日：2013-01-18
发明人： ROBINETT, Warren
IPC分类号： G11C5/02
CPC分类号： G11C13/0026 , G11C5/025 , G11C5/063 , G11C7/18 , G11C8/10 , G11C8/12 , G11C8/14 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2213/71
摘要： A computer readable memory includes a circuit layer, a multilayer memory stacked over the circuit layer to form a memory box, the memory box comprising a bottom surface interfacing with the circuit layer and four side surfaces, and a first switching crossbar array disposed on a first side of the memory box. A plurality of vias connects the circuit layer to the first switching crossbar layer. The first switching crossbar array accepts signals from the plurality of vias and selectively connects a crossbar in the multilayer memory to the circuit layer. A method for addressing multilayer memory is also provided.
摘要翻译： 一种计算机可读存储器，包括电路层，堆叠在所述电路层上以形成存储器盒的多层存储器，所述存储器盒包括与所述电路层和四个侧表面接口的底表面以及布置在第一开关交叉开关阵列上的第一开关交叉开关阵列 记忆盒的一面。 多个通孔将电路层连接到第一开关横杆层。 第一切换交叉开关阵列接受来自多个通孔的信号并选择性地将多层存储器中的交叉开关连接到电路层。 还提供了一种用于寻址多层存储器的方法。
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7.发明公开DEFECT-AND-FAILURE-TOLERANT DEMULTIPLEXER USING SERIES REPLICATION AND ERROR-CONTROL ENCODING 有权缺陷和容错信号分离器系列产品的复制和错误WATCHING编码
公开(公告)号：EP2038750A2
公开(公告)日：2009-03-25
申请号：EP07796813.9
申请日：2007-07-11
IPC分类号： G06F11/10 , H03K19/177
CPC分类号： H03K19/007 , G06F11/1076 , H03K19/00315
摘要： One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers (figures 14 an 16). This method is applicable to nanoscale, microscal, or larger-scale demultiplexer circuits,. Demultiplexer circuits can be viewed as a set of AND gates (figures 9A-B), each including a reversibly switchable interconnection between a number of address lines (910-912 and 920-922), or address-line-derived signal lines, and an output signal line (914 and 924). Each reversibly switchable interconnection includes one ot more reversibly switchable elements (906-908 and 916-918). In certain demultiplexer embodiments, NMOS (102) and/or PMOS transistors (206) are employed as reversibly switchable elements. In the method that representd one embodiment of the present invention, two or more serially connected transistors (410, 412, and 411, 413; 1502) are employed in each reversibly switchable interconnection, so that short defects in up to one less then the number of serially interconnected transistors does not lead to failure of the reversibly switchable interconnection. In addition, error-control-encoding techniques are used to introduce additional address-line-derived signal lines (1602, 1604) and additional switchable interconnections (1610) so that the demultiplexer may function even when a number of individual, switchable interconnections are open-defective.
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