公开(公告)号：EP0252206A3

公开(公告)日：1988-08-31

申请号：EP87101113

申请日：1987-01-27

申请人： HITACHI, LTD.

发明人： Homma, Hideo ,  Misawa, Yutaka ,  Momma, Naohiro

IPC分类号： H01L21/82 ,  H01L21/285 ,  H01L21/00

CPC分类号： H01L29/66272 ,  H01L21/0337 ,  H01L21/32137 ,  H01L21/8249 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/78

摘要： A method of fabricating a semiconductor device includes the steps of: forming at least one first semi­conductor region (51) of a first conductivity type and at least one second semiconductor region (50) of a second conductivity type in a main surface of a semiconductor layer of the first conductivity type; forming a three-layer film having a desired shape on each of the first and second semiconductor regions, the three-layer film being made up of a bottom layer which is a conductive film (56), an intermediate layer which is a silicon nitride film (57), and a top layer which is a polycrystalline silicon film (58) doped with one of arsenic and phosphorus; forming a first insulating layer (61) on the side wall of the three-layer film; forming a second polycrystalline silicon film (62) on the whole surface, and diffusing one of arsenic and phosphorus from the first polycrystal­line silicon film (58) into the second polycrystalline silicon film (62); selectively etching off the first polycrystalline silicon film (58) and that portion (62A) of the second polycrystalline silicon film, in which one of arsenic and phosphorus has been diffused; forming a second insulating layer (64) at least on the surface of that portion (63A) of the second polycrystalline silicon film which exists on the second semiconductor region (50); removing the silicon nitride film (57) and the conductive film (56) which exist on the second semiconductor region (50), while using the second insulating layer (64) as a mask, to form an aperture and forming a third polycrystalline silicon film (69) so that the aperture (68) is covered by the third polycrystalline silicon film.

公开(公告)号：EP0252206B1

公开(公告)日：1992-07-15

申请号：EP87101113.6

申请日：1987-01-27

申请人： HITACHI, LTD.

发明人： Homma, Hideo ,  Misawa, Yutaka ,  Momma, Naohiro

IPC分类号： H01L21/82 ,  H01L21/285 ,  H01L21/00

CPC分类号： H01L29/66272 ,  H01L21/0337 ,  H01L21/32137 ,  H01L21/8249 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/78

公开(公告)号：EP0252206A2

公开(公告)日：1988-01-13

申请号：EP87101113.6

申请日：1987-01-27

申请人： HITACHI, LTD.

发明人： Homma, Hideo ,  Misawa, Yutaka ,  Momma, Naohiro

IPC分类号： H01L21/82 ,  H01L21/285 ,  H01L21/00

CPC分类号： H01L29/66272 ,  H01L21/0337 ,  H01L21/32137 ,  H01L21/8249 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/78

摘要： A method of fabricating a semiconductor device includes the steps of: forming at least one first semi­conductor region (51) of a first conductivity type and at least one second semiconductor region (50) of a second conductivity type in a main surface of a semiconductor layer of the first conductivity type; forming a three-layer film having a desired shape on each of the first and second semiconductor regions, the three-layer film being made up of a bottom layer which is a conductive film (56), an intermediate layer which is a silicon nitride film (57), and a top layer which is a polycrystalline silicon film (58) doped with one of arsenic and phosphorus; forming a first insulating layer (61) on the side wall of the three-layer film; forming a second polycrystalline silicon film (62) on the whole surface, and diffusing one of arsenic and phosphorus from the first polycrystal­line silicon film (58) into the second polycrystalline silicon film (62); selectively etching off the first polycrystalline silicon film (58) and that portion (62A) of the second polycrystalline silicon film, in which one of arsenic and phosphorus has been diffused; forming a second insulating layer (64) at least on the surface of that portion (63A) of the second polycrystalline silicon film which exists on the second semiconductor region (50); removing the silicon nitride film (57) and the conductive film (56) which exist on the second semiconductor region (50), while using the second insulating layer (64) as a mask, to form an aperture and forming a third polycrystalline silicon film (69) so that the aperture (68) is covered by the third polycrystalline silicon film.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体层的主表面中形成至少一个第一导电类型的第一半导体区域（51）和第二导电类型的至少一个第二半导体区域（50） 的第一导电类型; 在第一和第二半导体区域中的每一个上形成具有期望形状的三层膜，三层膜由作为导电膜（56）的底层构成，作为氮化硅膜的中间层 （57），以及掺杂有砷和磷之一的多晶硅膜（58）的顶层; 在所述三层膜的侧壁上形成第一绝缘层（61）; 在整个表面上形成第二多晶硅膜（62），并将砷和磷中的一种从第一多晶硅膜（58）扩散到第二多晶硅膜（62）中; 选择性地蚀刻出第一多晶硅膜（58）和砷和磷之一已被扩散的第二多晶硅膜的部分（62A）; 至少在所述第二半导体区域（50）上存在的所述第二多晶硅膜的所述部分（63A）的表面上形成第二绝缘层（64）; 在使用第二绝缘层（64）作为掩模的同时，移除存在于第二半导体区域（50）上的氮化硅膜（57）和导电膜（56），以形成孔并形成第三多晶硅膜 （69），使得孔（68）被第三多晶硅膜覆盖。

公开(公告)号：EP0256397B1

公开(公告)日：1992-02-19

申请号：EP87111116.7

申请日：1987-07-31

申请人： HITACHI, LTD.

发明人： Homma, Hideo ,  Misawa, Yutaka ,  Momma, Naohiro

IPC分类号： H01L21/74 ,  H01L21/20 ,  H01L21/76 ,  H01L29/72

CPC分类号： H01L21/2007 ,  H01L21/74 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/76297 ,  H01L29/7325

公开(公告)号：EP0256397A1

公开(公告)日：1988-02-24

申请号：EP87111116.7

申请日：1987-07-31

申请人： HITACHI, LTD.

发明人： Homma, Hideo ,  Misawa, Yutaka ,  Momma, Naohiro

IPC分类号： H01L21/74 ,  H01L21/20 ,  H01L21/76 ,  H01L29/72

CPC分类号： H01L21/2007 ,  H01L21/74 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/76297 ,  H01L29/7325

摘要： A semiconductor device has a structure in which two semiconductor substrates (1, 2) are coupled to each other through a semiconductor oxide film (3) and a metal silicide film (9), and a semiconductor element, for example, a bi-polar transistor is formed in the semicon­ductor substrate (2) on the metal silicide film side, whereby a metal silicide layer (9) having a high melting point is provided beneath one region of the bi-polar transistor for example, an n⁺ buried collector layer (5) and in ohmic contact with the n⁺ buried collector layer. An electrical isolation between the adjacent semiconduc­tor elements is made by an insulating layer (12, 18).

摘要翻译： 半导体器件具有其中两个半导体衬底（1,2）通过半导体氧化膜（3）和金属硅化物膜（9）彼此耦合的结构，以及半导体元件，例如双极性 晶体管形成在金属硅化物膜侧的半导体衬底（2）中，由此例如在双极晶体管的一个区域的下方设置具有高熔点的金属硅化物层（9），n +掩埋 集电极层（5）并与n +掩埋的集电极层欧姆接触。 相邻的半导体元件之间的电绝缘由绝缘层（12,18）制成。