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公开(公告)号：EP2972891B1
公开(公告)日：2020-05-06
申请号：EP13877967.3
申请日：2013-03-14
发明人： YOON, Doe Hyun , LI, Sheng , ZHAO, Jishen , JOUPPI, Norman Paul
IPC分类号： G06F12/08 , G06F3/06 , G06F12/0868 , G06F12/0897 , G06F12/0804 , G06F12/0815 , G06F9/46
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公开(公告)号：EP2842036B1
公开(公告)日：2019-07-03
申请号：EP12875252.4
申请日：2012-04-27
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公开(公告)号：EP3028277A1
公开(公告)日：2016-06-08
申请号：EP13890792.8
申请日：2013-07-31
CPC分类号： G06F21/79 , G06F21/72 , G11C7/1006 , G11C7/24 , G11C11/4078 , G11C13/0004 , G11C13/0059 , G11C14/0036
摘要： According to an example, a hybrid secure non-volatile main memory (HSNVMM) may include a non-volatile memory (NVM) to store a non-working set of memory data in an encrypted format, and a dynamic random-access memory (DRAM) buffer to store a working set of memory data in a decrypted format. A cryptographic engine may selectively encrypt and decrypt memory pages in the working and non-working sets of memory data. A security controller may control memory data placement and replacement in the NVM and the DRAM buffer based on memory data characteristics that include clean memory pages, dirty memory pages, working set memory pages, and non-working set memory pages. The security controller may further provide incremental encryption and decryption instructions to the cryptographic engine based on the memory data characteristics.
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公开(公告)号：EP3028151A1
公开(公告)日：2016-06-08
申请号：EP13890511.2
申请日：2013-07-31
发明人： YOON, Doe Hyun , KELLY, Terence P. , CHANG, Jichuan , MURALIMANOHAR, Naveen , SCHREIBER, Robert , RANGANATHAN, Parthasarathy
IPC分类号： G06F12/00
CPC分类号： G06F11/1451 , G06F3/0614 , G06F3/0628 , G06F11/1072 , G06F11/1435 , G06F11/1471 , G06F2201/84 , G11C29/52
摘要： According to an example, versioned memory implementation may include comparing a global memory version to a block memory version. The global memory version may correspond to a plurality of memory blocks, and the block memory version may correspond to one of the plurality of memory blocks. A subblock-bit-vector (SBV) corresponding to a plurality of subblocks of the one of the plurality of memory blocks may be evaluated. Based on the comparison and the evaluation, a determination may be made as to which level in a cell of one of the plurality of subblocks of the one of the plurality of memory blocks checkpoint data is stored.
摘要翻译： 根据示例，版本化存储器实现可以包括将全局存储器版本与块存储器版本进行比较。 全局存储器版本可以对应于多个存储器块，并且块存储器版本可以对应于多个存储器块中的一个。 可以评估与多个存储块中的一个的多个子块相对应的子块位向量（SBV）。 基于比较和评估，可以确定多个存储块中的一个存储块检查点数据的多个子块中的一个的子单元中的哪个级别被存储。
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公开(公告)号：EP2926341B1
公开(公告)日：2020-02-19
申请号：EP12889067.0
申请日：2012-11-30
发明人： YOON, Doe Hyun , SCHREIBER, Robert , LI, Sheng
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公开(公告)号：EP2915045B1
公开(公告)日：2019-01-02
申请号：EP12887804.8
申请日：2012-11-02
发明人： LI, Sheng , JOUPPI, Norman Paul , YOON, Doe Hyun
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公开(公告)号：EP3005128B1
公开(公告)日：2018-07-04
申请号：EP13885796.6
申请日：2013-05-30
发明人： YOON, Doe Hyun , LI, Sheng , CHANG, Jichuan , CHEN, Ke , RANGANATHAN, Parthasarathy , JOUPPI, Norman Paul
CPC分类号： G06F3/0611 , G06F3/0646 , G06F3/0683 , G06F13/1636 , G06F13/1668 , G06F13/1689 , G06F13/1694 , G06F13/4243
摘要： A first memory controller receives an access command from a second memory controller, where the access command is timing non-deterministic with respect to a timing specification of a memory. The first memory controller sends at least one access command signal corresponding to the access command to the memory, wherein the at least one access command signal complies with the timing specification. The first memory controller determines a latency of access of the memory. The first memory controller sends feedback information relating to the latency to the second memory controller.
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公开(公告)号：EP2820548B1
公开(公告)日：2016-12-14
申请号：EP12869720.8
申请日：2012-03-02
发明人： YOON, Doe Hyun , CHANG, Jichuan , MURALIMANOHAR, Naveen , SCHREIBER, Robert , FARABOSCHI, Paolo , RANGANATHAN, Parthasarathy
CPC分类号： G06F11/1407 , G06F11/1072 , G06F11/1435 , G06F11/1451 , G06F11/1471 , G06F12/0238 , G06F2212/1016 , G06F2212/1032 , G06F2212/7202 , G06F2212/7209 , G11C11/5621 , G11C2211/5641
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9.发明公开LOOKUP OF A DATA STRUCTURE CONTAINING A MAPPING BETWEEN A VIRTUAL ADDRESS SPACE AND A PHYSICAL ADDRESS SPACE 审中-公开搜索在数据结构之间的虚拟地址空间和物理地址空间分配
公开(公告)号：EP3017374A1
公开(公告)日：2016-05-11
申请号：EP13888862.3
申请日：2013-07-01
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/0802 , G06F12/0875 , G06F12/1027 , G06F12/1054 , G06F12/1063 , G06F2212/1021 , G06F2212/452 , G06F2212/50 , G06F2212/68 , G06F2212/681
摘要： A memory region stores a data structure that contains a mapping between a virtual address space and a physical address space of a memory. A portion of the mapping is cached in a cache memory. In response to a miss in the cache memory responsive to a lookup of a virtual address of a request, an indication is sent to the buffer device. In response to the indication, a hardware controller on the buffer device performs a lookup of the data structure in the memory region to find a physical address corresponding to the virtual address.
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公开(公告)号：EP3005128A1
公开(公告)日：2016-04-13
申请号：EP13885796.6
申请日：2013-05-30
发明人： YOON, Doe Hyun , LI, Sheng , CHANG, Jichuan , CHEN, Ke , RANGANATHAN, Parthasarathy , JOUPPI, Norman Paul
CPC分类号： G06F3/0611 , G06F3/0646 , G06F3/0683 , G06F13/1636 , G06F13/1668 , G06F13/1689 , G06F13/1694 , G06F13/4243
摘要： A first memory controller receives an access command from a second memory controller, where the access command is timing non-deterministic with respect to a timing specification of a memory. The first memory controller sends at least one access command signal corresponding to the access command to the memory, wherein the at least one access command signal complies with the timing specification. The first memory controller determines a latency of access of the memory. The first memory controller sends feedback information relating to the latency to the second memory controller.
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