公开(公告)号：EP3073384B1

公开(公告)日：2018-10-10

申请号：EP16162354.1

申请日：2016-03-24

Applicant: Kove IP, LLC

Inventor： STABRAWA, Timothy A. ,  POLING, Andrew S. ,  CORNELIUS, Zachary A. ,  TAYLOR, Jesse I. ,  OVERTON, John

IPC: G06F12/10 ,  G06F12/08 ,  G06F3/06 ,  G06F9/50

CPC classification number: G06F3/0605 ,  G06F3/0614 ,  G06F3/0643 ,  G06F3/0667 ,  G06F3/067 ,  G06F3/0673 ,  G06F9/5016 ,  G06F12/08 ,  G06F12/10 ,  G06F2212/1004 ,  G06F2212/1048 ,  G06F2212/154 ,  G06F2212/50 ,  G06F2212/657 ,  Y02D10/13

Abstract: Methods and systems are provided for fork-safe memory allocation from memory-mapped files. A child process may be provided a memory mapping at a same virtual address as a parent process, but the memory mapping may map the virtual address to a different location within a file than for the parent process.

公开(公告)号：EP3364286A1

公开(公告)日：2018-08-22

申请号：EP17202431.7

申请日：2012-08-11

Applicant: Pure Storage, Inc.

Inventor： COLGROVE, John ,  HAYES, John ,  MILLER, Ethan ,  WANG, Feng

IPC: G06F3/06 ,  G06F11/14 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/1009

CPC classification number: G06F12/0246 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0638 ,  G06F3/0665 ,  G06F3/067 ,  G06F12/0802 ,  G06F12/1009 ,  G06F2212/50 ,  G06F2212/7201

Abstract: A system and method for efficiently performing user storage virtualization for data stored in a storage system including a plurality of solid-state storage devices. A data storage subsystem supports multiple mapping tables. Records within a mapping table are arranged in multiple levels. Each level stores pairs of a key value and a pointer value. The levels are sorted by time. New records are inserted in a created newest (youngest) level. No edits are performed in-place. All levels other than the youngest may be read only. The system may further include an overlay table which identifies those keys within the mapping table that are invalid.

公开(公告)号：EP3335123A1

公开(公告)日：2018-06-20

申请号：EP16741782.3

申请日：2016-07-13

Applicant: Qualcomm Incorporated

Inventor： OPORTUS VALENZUELA, Andres Alejandro ,  CHHABRA, Gurvinder Singh ,  GENG, Nieyan ,  BRENNEN JR., John Francis ,  CHINTAMNEEDI, BalaSubrahmanyam

IPC: G06F12/1027 ,  G06F12/02 ,  G06F12/04

CPC classification number: G06F12/1036 ,  G06F12/023 ,  G06F12/0253 ,  G06F12/04 ,  G06F12/1027 ,  G06F2212/1044 ,  G06F2212/50

Abstract: Systems and methods pertain to a method of memory management. Gaps are unused portions of a physical memory in sections of the physical memory mapped to virtual addresses by entries of a translation look-aside buffer (TLB). Sizes and alignment of the sections in the physical memory may be based on the number of entries in the TLB, which leads to the gaps. One or more gaps identified in the physical memory are reclaimed or reused, where the one or more gaps are collected to form a dynamic buffer, by mapping physical addresses of the gaps to virtual addresses of the dynamic buffer.

公开(公告)号：EP2842031A4

公开(公告)日：2015-12-30

申请号：EP12875296

申请日：2012-04-25

Applicant: INTEL CORP

Inventor： GANAPATHI RAVINDRA BABU ,  CHEN HU

IPC: G06F9/50 ,  G06F12/08

CPC classification number: G06F12/1009 ,  G06F3/0614 ,  G06F3/0655 ,  G06F3/0671 ,  G06F12/08 ,  G06F12/0822 ,  G06F12/128 ,  G06F13/1663 ,  G06F2212/50 ,  G06F2212/6026 ,  G06F2212/621 ,  G06F2212/65 ,  G06F2212/657

公开(公告)号：EP3238073A4

公开(公告)日：2017-12-13

申请号：EP15874355

申请日：2015-12-22

Applicant: TEXAS INSTRUMENTS INC

Inventor： VENKATASUBRAMANIAN RAMAKRISHNAN ,  OLORODE OLULEYE ,  RAMAPRASAD BIPIN PRASAD HEREMAGALUR

IPC: G06F12/08

CPC classification number: G06F12/1045 ,  G06F2212/1021 ,  G06F2212/50 ,  G06F2212/654 ,  G06F2212/681

Abstract: This invention hides the page miss translation latency for program fetches. In this invention whenever an access is requested by CPU, the L1I cache controller does a-priori lookup of whether the virtual address plus the fetch packet count of expected program fetches crosses a page boundary. If the access crosses a page boundary, the L1I cache controller will request a second page translation along with the first page. This pipelines requests to the μTLB without waiting for L1I cache controller to begin processing the second page requests. This becomes a deterministic prefetch of the second page translation request. The translation information for the second page is stored locally in L1I cache controller and used when the access crosses the page boundary.

公开(公告)号：EP3060993A1

公开(公告)日：2016-08-31

申请号：EP14792704.0

申请日：2014-10-21

Applicant: Marvell World Trade Ltd.

Inventor： SUTARDJA, Sehat

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0638 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/0683 ,  G06F9/4406 ,  G06F12/0804 ,  G06F12/0813 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/10 ,  G06F12/1027 ,  G06F2003/0691 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/152 ,  G06F2212/154 ,  G06F2212/161 ,  G06F2212/171 ,  G06F2212/20 ,  G06F2212/202 ,  G06F2212/214 ,  G06F2212/22 ,  G06F2212/222 ,  G06F2212/251 ,  G06F2212/305 ,  G06F2212/50 ,  G06F2212/60 ,  G06F2212/6022 ,  G06F2212/6032 ,  G06F2212/608 ,  G06F2212/62 ,  G11C11/40607 ,  Y02D10/13

Abstract: A data access system including a processor and a final level cache module. The processor is configured to generate a request to access a first physical address. The final level cache module includes a dynamic random access memory (DRAM), a final level cache controller, and a DRAM controller. The final level cache controller is configured to (i) receive the request from the processor, and (ii) convert the first physical address to a first virtual address. The DRAM controller is configured to (i) convert the first virtual address to a second physical address, and (ii) access the DRAM based on the second physical address.

Abstract translation: 包括处理器和最终级缓存模块的数据访问系统。 处理器被配置为生成访问第一物理地址的请求。 最终级缓存模块包括动态随机存取存储器（DRAM），最终级高速缓存控制器和DRAM控制器。 最终级缓存控制器被配置为（i）从处理器接收请求，以及（ii）将第一物理地址转换为第一虚拟地址。 DRAM控制器被配置为（i）将第一虚拟地址转换为第二物理地址，以及（ii）基于第二物理地址访问DRAM。

公开(公告)号：EP3017374A1

公开(公告)日：2016-05-11

申请号：EP13888862.3

申请日：2013-07-01

Applicant: Hewlett-Packard Enterprise Development LP

Inventor： MURALIMANOHAR, Naveen ,  LIM, Kevin T. ,  JOUPPI, Norman Paul ,  YOON, Doe Hyun

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F12/0802 ,  G06F12/0875 ,  G06F12/1027 ,  G06F12/1054 ,  G06F12/1063 ,  G06F2212/1021 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/68 ,  G06F2212/681

Abstract: A memory region stores a data structure that contains a mapping between a virtual address space and a physical address space of a memory. A portion of the mapping is cached in a cache memory. In response to a miss in the cache memory responsive to a lookup of a virtual address of a request, an indication is sent to the buffer device. In response to the indication, a hardware controller on the buffer device performs a lookup of the data structure in the memory region to find a physical address corresponding to the virtual address.

公开(公告)号：EP2441005A2

公开(公告)日：2012-04-18

申请号：EP10734026.7

申请日：2010-06-09

Applicant: Vorbach, Martin

Inventor： VORBACH, Martin

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F9/526 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0893 ,  G06F2212/271 ,  G06F2212/50 ,  G06F2212/62 ,  Y02D10/13

Abstract: The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said at least two cores, preferably at least four processor cores, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at least one node, preferably at least three nodes for a four processor core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.

公开(公告)号：EP3304320A1

公开(公告)日：2018-04-11

申请号：EP16720680.4

申请日：2016-04-27

Applicant: Qualcomm Incorporated

Inventor： PODAIMA, Jason Edward ,  WIERCIENSKI, Paul Christopher John ,  MOREIRA, Carlos Javier ,  MIRETSKY, Alexander ,  VARIA, Meghal ,  ERNEWEIN, Kyle John ,  SOMASUNDARAM, Manokanthan ,  CHOUDRY, Muhammad Umar ,  GADELRAB, Serag Monier

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F12/1063 ,  G06F12/0806 ,  G06F12/0842 ,  G06F12/0844 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/1036 ,  G06F2212/1024 ,  G06F2212/50 ,  G06F2212/655 ,  G06F2212/682 ,  G06F2212/683 ,  G06F2212/684

Abstract: Systems and methods relate to performing address translations in a multithreaded memory management unit (MMU). Two or more address translation requests can be received by the multithreaded MMU and processed in parallel to retrieve address translations to addresses of a system memory. If the address translations are present in a translation cache of the multithreaded MMU, the address translations can be received from the translation cache and scheduled for access of the system memory using the translated addresses. If there is a miss in the translation cache, two or more address translation requests can be scheduled in two or more translation table walks in parallel.

公开(公告)号：EP3238073A1

公开(公告)日：2017-11-01

申请号：EP15874355.9

申请日：2015-12-22

Applicant: Texas Instruments Incorporated

Inventor： VENKATASUBRAMANIAN, Ramakrishnan ,  OLORODE, Oluleye ,  RAMAPRASAD, Bipin Prasad, Heremagalur

IPC: G06F12/08

CPC classification number: G06F12/1045 ,  G06F2212/1021 ,  G06F2212/50 ,  G06F2212/654 ,  G06F2212/681

Abstract: Example embodiments hide the page miss translation latency for program fetches. In example embodiments, whenever an access is requested by a CPU, the L1l cache controller (111) does a-priori lookup of whether the virtual address plus the fetch packet count of expected program fetches crosses a page boundary (1614, 1622). If the access crosses a page boundary (1622), the L1l cache controller (111) will request a second page translation along with the first page. This pipelines requests to the μΤLΒ (1501) without waiting for L1l cache controller (111) to begin processing the second page requests. This becomes a deterministic prefetch of the second page translation request. The translation information for the second page is stored (1624) locally in L1l cache controller (111) and used when the access crosses the page boundary.

Abstract translation: 示例实施例隐藏程序提取的页面未命中翻译等待时间。 在示例实施例中，每当CPU请求访问时，L1 1高速缓存控制器（111）先前查找虚拟地址加预期程序提取的提取包计数是否跨页面边界（1614,1622）。 如果访问跨越页边界（1622），则L1l高速缓存控制器（111）将连同第一页一起请求第二页翻译。 该流水线向μTBL（1501）发送请求而不等待L1L高速缓存控制器（111）开始处理第二页面请求。 这成为第二页翻译请求的确定性预取。 第二页的翻译信息在L1l高速缓存控制器（111）中本地存储（1624），并在访问跨越页面边界时使用。