公开(公告)号：EP2140458A4

公开(公告)日：2010-05-05

申请号：EP07867608

申请日：2007-12-04

Applicant: IBM

Inventor： GAIDIS MICHAEL C ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  DEBROSSE JOHN K ,  HSU LOUIS L C ,  RADENS CARL ,  WONG KEITH K H ,  YANG CHIH-CHAO

IPC: G11C19/08 ,  G11B5/008

CPC classification number: G11C19/0841 ,  B82Y10/00 ,  G11C5/02 ,  G11C11/161 ,  G11C11/1675 ,  Y10T29/53165

公开(公告)号：EP1908076A4

公开(公告)日：2009-06-17

申请号：EP06737703

申请日：2006-03-09

Applicant: IBM

Inventor： HSU LOUIS L C ,  JI BRIAN L ,  LAM CHUNG HON ,  WONG HON-SUM PHILIP

IPC: G11C11/24

CPC classification number: G11C13/0004 ,  G11C15/046

Abstract: A non- volatile content addressable memory cell comprises: a first phase change material element, the first phase change material element having one end connected to a match-line; a first transistor, the first transistor having a gate connected to a word-line, a source connected to a true bit-read- write-search-line, and a drain connected to another end of the first phase change material element; a second phase change material element, the second phase change material element having one end connected to the match-line; and a second transistor, the second transistor having a gate connected to the word-line, a source connected to a complementary bit- read-write-search-line, and a drain connected to another end of the second phase change material element.

公开(公告)号：EP1911096A4

公开(公告)日：2008-10-22

申请号：EP06788341

申请日：2006-07-24

Applicant: IBM

Inventor： DALTON TIMOTHY J ,  HSU LOUIS L C ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO ,  GAIDIS MICHAEL C ,  RADENS CARL ,  CLEVENGER LAWRENCE A

IPC: H01L27/22 ,  H01L21/768 ,  H01L21/8247 ,  H01L23/528 ,  H01L43/12

CPC classification number: B82Y10/00 ,  H01L27/222 ,  H01L43/12

Abstract: A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.