Abstract:
A metal-insulator-metal (MIM) capacitor (242/252) structure and method of forming the same. A dielectric layer (214) of a semiconductor device (200) is patterned with a dual damascene pattern having a first pattern (216) and a second pattern (218). The second pattern (218) has a greater depth than the first pattern (216). A conductive layer (226) is formed over the dielectric layer (214) in the first pattern, and a conductive layer is formed over the conductive layer in the first pattern (216). A dielectric layer (232), conductive layer (234), dielectric layer (236) and conductive layer (238) are disposed over the conductive layer (226) of the second pattern (218). Conductive layer (234), dielectric layer (232) and conductive layer (226) form a first MIM capacitor (252). Conductive layer (238), dielectric layer (236) and conductive layer (234) form a second MIM capacitor (242) parallel to the first MIM capacitor (242).
Abstract:
A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.