公开(公告)号：EP4381383A1

公开(公告)日：2024-06-12

申请号：EP21952174.7

申请日：2021-08-03

申请人： Intel Corporation

发明人： NACHIMUTHU, Murugasamy K. ,  WU, Yidong ,  WU, Jiaxin ,  LI, Ruixia

IPC分类号： G06F9/44

CPC分类号： G06F8/65

公开(公告)号：EP3731090A1

公开(公告)日：2020-10-28

申请号：EP20163760.0

申请日：2020-03-17

申请人： Intel Corporation

发明人： NACHIMUTHU, Murugasamy K. ,  SEN, Sujoy

IPC分类号： G06F9/50 ,  H04L12/24 ,  H04L12/26 ,  H04L29/08 ,  G06F11/30 ,  G06F11/34

摘要： Technologies for providing resource health based node composition and management include a compute device having circuitry configured to receive status data from each of multiple resources in a system. The status data is indicative of an ability of the corresponding resource to be utilized in the execution of a workload. The circuitry is also configured to determine, as a function of the received status data, a responsive action to be performed to manage execution of the workload. Further, the circuitry is configured to perform the responsive action to manage execution of the workload.

公开(公告)号：EP2519892A2

公开(公告)日：2012-11-07

申请号：EP10841477.2

申请日：2010-12-10

申请人： Intel Corporation

发明人： NACHIMUTHU, Murugasamy K. ,  KUMAR, Mohan J. ,  WANG, Chung-Chi

IPC分类号： G06F15/177

CPC分类号： G06F15/7871

摘要： In some embodiments system reconfiguration code and data to be used to perform a dynamic hardware reconfiguration of a system including a plurality of processor cores is cached and any direct or indirect memory accesses during the dynamic hardware reconfiguration are prevented. One of the processor cores executes the cached system reconfiguration code and data in order to dynamically reconfigure the hardware. Other embodiments are described and claimed.

公开(公告)号：EP3441885B1

公开(公告)日：2020-11-25

申请号：EP18182324.6

申请日：2018-07-06

申请人： INTEL Corporation

发明人： SWAMINATHAN, Muthukumar P. ,  NACHIMUTHU, Murugasamy K. ,  NATU, Mahesh S.

IPC分类号： G06F12/02

公开(公告)号：EP3719637A2

公开(公告)日：2020-10-07

申请号：EP20158894.4

申请日：2020-02-21

申请人： INTEL Corporation

发明人： NACHIMUTHU, Murugasamy K. ,  KUMAR, Mohan J. ,  DATTA, Shamanna M.

IPC分类号： G06F8/654 ,  G06F8/656 ,  G06F8/61 ,  G06F9/4401 ,  G06F11/14

摘要： An interface is provided to update a firmware of a persistent memory module at runtime without restarting an operating system on the platform. The operating system initiates the firmware update by triggering a sleep state or by entering a soft reboot. The interface is capable of preserving the state of the platform for all memory modes that support volatile memory regions, persistent memory regions, or both, and reducing or eliminating the demand for access to memory during the firmware update. The persistent memory module is capable of updating the firmware responsive to a platform instruction generated using the interface, including preserving operational states for memory devices in all memory regions, including memory devices in volatile and persistent memory regions.

公开(公告)号：EP3161639A1

公开(公告)日：2017-05-03

申请号：EP15814715.7

申请日：2015-05-28

申请人： Intel Corporation

发明人： KUMAR, Mohan J. ,  NACHIMUTHU, Murugasamy K. ,  RAAD, Camille C.

IPC分类号： G06F11/07 ,  G06F9/22

CPC分类号： G06F11/073 ,  G06F11/0769 ,  G06F11/0787 ,  G09C1/00 ,  G11C5/04 ,  G11C29/52 ,  G11C2029/0409

摘要： Examples may include a basic input/output system (BIOS) for a computing platform communicating with a controller for a non-volatile dual in-line memory module (NVDIMM). Communication between the BIOS and the controller may include a request for the controller to scan and identify error locations in non-volatile memory at the NVDIMM. The non-volatile memory may be capable of providing persistent memory for the NVDIMM.

摘要翻译： 示例可以包括用于与用于非易失性双列直插式存储器模块（NVDIMM）的控制器通信的计算平台的基本输入/输出系统（BIOS）。 BIOS与控制器之间的通信可以包括请求控制器扫描并识别NVDIMM处的非易失性存储器中的错误位置。 非易失性存储器可能能够为NVDIMM提供持久存储器。

公开(公告)号：EP3161622A1

公开(公告)日：2017-05-03

申请号：EP15810867.0

申请日：2015-06-01

申请人： Intel Corporation

发明人： RAMANUJAN, Raj K. ,  SANKARAN, Rajesh M. ,  NACHIMUTHU, Murugasamy K. ,  MANGOLD, Richard P.

IPC分类号： G06F9/44 ,  G06F12/02

CPC分类号： G06F3/0611 ,  G06F3/0625 ,  G06F3/0632 ,  G06F3/0679 ,  G06F8/71 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4416 ,  G06F11/1417 ,  G06F11/3476 ,  G11C7/20

摘要： Methods and apparatus to accelerate boot time zeroing of memory based on Non-Volatile Memory (NVM) technology are described. In an embodiment, a storage device stores a boot version number corresponding to a portion of a non-volatile memory. A memory controller logic causes an update of the stored boot version number in response to each subsequent boot event. The memory controller logic returns a zero in response to a read operation directed at the portion of the non-volatile memory and a mismatch between the stored boot version number and a current boot version number. Other embodiments are also disclosed and claimed.

摘要翻译： 的方法和装置，以加速引导时间的基于非易失性存储器（NVM）技术存储器调零进行说明。 ，实施例中的存储装置存储引导版本号对应于非易失性存储器的一部分。 存储器控制器逻辑使得响应于每个船随后发生的事件所存储的引导版本号的更新。 存储器控制器逻辑响应于读取手术针对非易失性存储器的所述部分与所存储的引导版本号和当前引导的版本号之间不匹配返回零。 其它实施例因此是游离缺失盘和要求保护的。

公开(公告)号：EP3719637A3

公开(公告)日：2021-01-06

申请号：EP20158894.4

申请日：2020-02-21

申请人： INTEL Corporation

发明人： NACHIMUTHU, Murugasamy K. ,  KUMAR, Mohan J. ,  DATTA, Shamanna M.

IPC分类号： G06F8/654 ,  G06F8/656 ,  G06F8/61 ,  G06F9/4401 ,  G06F11/14

摘要： An interface is provided to update a firmware of a persistent memory module at runtime without restarting an operating system on the platform. The operating system initiates the firmware update by triggering a sleep state or by entering a soft reboot. The interface is capable of preserving the state of the platform for all memory modes that support volatile memory regions, persistent memory regions, or both, and reducing or eliminating the demand for access to memory during the firmware update. The persistent memory module is capable of updating the firmware responsive to a platform instruction generated using the interface, including preserving operational states for memory devices in all memory regions, including memory devices in volatile and persistent memory regions.

公开(公告)号：EP2973571B1

公开(公告)日：2020-04-22

申请号：EP13877923.6

申请日：2013-03-15

申请人： Intel Corporation

发明人： NALE, Bill ,  JASPER, Jonathan C. ,  LOVELACE, John V. ,  NACHIMUTHU, Murugasamy K. ,  ZHU, Jun ,  QUACH, Tuan M.

IPC分类号： G11C7/10 ,  G11C7/22 ,  G06F13/14

公开(公告)号：EP3304326A1

公开(公告)日：2018-04-11

申请号：EP16803988.1

申请日：2016-05-19

申请人： INTEL Corporation

发明人： VERGIS, George ,  BAINS, Kuljit S. ,  MCCALL, James A. ,  NACHIMUTHU, Murugasamy K. ,  KUMAR, Mohan J.

IPC分类号： G06F13/16 ,  G06F9/30 ,  G06F12/06 ,  G06F12/02 ,  G06F3/06

CPC分类号： G06F12/02 ,  G11C5/04 ,  G11C11/40615 ,  G11C11/4074 ,  G11C2211/4067

摘要： A system enables memory device specific self-refresh entry and exit commands. When memory devices on a shared control bus (such as all memory devices in a rank) are in self-refresh, a memory controller can issue a device specific command with a self-refresh exit command and a unique memory device identifier to the memory device. The controller sends the command over the shared control bus, and only the selected, identified memory device will exit self-refresh while the other devices will ignore the command and remain in self-refresh. The controller can then execute data access over a shared data bus with the specific memory device while the other memory devices are in self-refresh.