公开(公告)号：EP2852088A1

公开(公告)日：2015-03-25

申请号：EP14169143.6

申请日：2008-03-25

申请人： Intel Corporation

发明人： Gueron, Shay ,  Feghali, Wajdi ,  Gopal, Vinodh ,  Raghunandan, Makaram ,  Dixon, Martin ,  Chennupaty, Srinivas ,  Kounavis, Michael

IPC分类号： H04L9/06 ,  H04L9/08

CPC分类号： H04L9/0631 ,  G06F3/0623 ,  G06F3/0665 ,  G06F3/0689 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/30178 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3887 ,  G06F9/3895 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1408 ,  G06F21/602 ,  G06F2212/1052 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2212/454 ,  G06F2212/602 ,  G11C7/1072 ,  H04L9/0816 ,  H04L9/0861 ,  H04L2209/12 ,  H04L2209/24

摘要： Methods and devices for use with the advanced encryption standard (AES) are presented including a processor comprising a decode unit to decode a single round encryption instruction to perform an AES single round encryption operation, wherein the single round encryption instruction specifies a destination register to store 128-bit input data and a source register to store a 128-bit round key; and an execution unit to execute micro-operations based on the single round encryption instruction, wherein the execution unit is to receive the 128-bit input data and the 128-bit round key, and wherein the execution unit is to perform the AES single round encryption operation on the 128-bit input data using the round key and to store 128-bit result data in the destination register.

摘要翻译： 提供了与高级加密标准（AES）一起使用的方法和装置，包括：处理器，包括解码单元，用于解码单循环加密指令以执行AES单循环加密操作，其中单轮加密指令指定目的地寄存器以存储 128位输入数据和源寄存器，用于存储128位圆键; 以及执行单元，用于基于所述单轮加密指令执行微操作，其中所述执行单元将接收所述128位输入数据和所述128位循环密钥，并且其中所述执行单元执行所述AES单回合 使用循环密钥对128位输入数据进行加密操作，并将128位结果数据存储在目标寄存器中。

公开(公告)号：EP2009543B1

公开(公告)日：2010-03-03

申请号：EP08251201.3

申请日：2008-03-28

申请人： Intel Corporation

发明人： Gueron, Shay ,  Kounavis, Michael

IPC分类号： G06F7/72

CPC分类号： G06F7/724 ,  H04L9/0631 ,  H04L9/0643 ,  H04L9/3242 ,  H04L2209/043

公开(公告)号：EP4002131A3

公开(公告)日：2022-08-10

申请号：EP21198156.8

申请日：2021-09-22

申请人： INTEL Corporation

发明人： Kounavis, Michael ,  Chhabra, Siddhartha ,  Durham, David M.

IPC分类号： G06F12/0868

摘要： Techniques and mechanisms for metadata, which corresponds to cached data, to be selectively stored to a sequestered memory region. In an embodiment, integrated circuitry evaluates whether a line of a cache can accommodate a first representation of both the data and some corresponding metadata. Where the cache line can accommodate the first representation, said first representation is generated and stored to the line. Otherwise, a second representation of the data is generated and stored to a cache line, and the metadata is stored to a sequestered memory region that is external to the cache. The cache line include an indication as to whether the metadata is represented in the cache line, or is stored in the sequestered memory region. In another embodiment, a metric of utilization of the sequestered memory region is provided to software which determines whether a capacity of the sequestered memory region is to be modified.

公开(公告)号：EP2852088B1

公开(公告)日：2019-02-06

申请号：EP14169143.6

申请日：2008-03-25

申请人： Intel Corporation

发明人： Gueron, Shay ,  Feghali, Wajdi ,  Gopal, Vinodh ,  Raghunandan, Makaram ,  Dixon, Martin ,  Chennupaty, Srinivas ,  Kounavis, Michael

IPC分类号： H04L9/06 ,  H04L9/08 ,  G06F3/06 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/14 ,  G06F21/60 ,  G11C7/10

公开(公告)号：EP4002131A2

公开(公告)日：2022-05-25

申请号：EP21198156.8

申请日：2021-09-22

申请人： INTEL Corporation

发明人： Kounavis, Michael ,  Chhabra, Siddhartha ,  Durham, David M.

IPC分类号： G06F12/0868

摘要： Techniques and mechanisms for metadata, which corresponds to cached data, to be selectively stored to a sequestered memory region. In an embodiment, integrated circuitry evaluates whether a line of a cache can accommodate a first representation of both the data and some corresponding metadata. Where the cache line can accommodate the first representation, said first representation is generated and stored to the line. Otherwise, a second representation of the data is generated and stored to a cache line, and the metadata is stored to a sequestered memory region that is external to the cache. The cache line include an indication as to whether the metadata is represented in the cache line, or is stored in the sequestered memory region. In another embodiment, a metric of utilization of the sequestered memory region is provided to software which determines whether a capacity of the sequestered memory region is to be modified.

公开(公告)号：EP2009543A1

公开(公告)日：2008-12-31

申请号：EP08251201.3

申请日：2008-03-28

申请人： Intel Corporation

发明人： Gueron, Shay ,  Kounavis, Michael

IPC分类号： G06F7/72

CPC分类号： G06F7/724 ,  H04L9/0631 ,  H04L9/0643 ,  H04L9/3242 ,  H04L2209/043

摘要： Methods and apparatus to speed up Galois Counter Mode (GCM) computations are described. In one embodiment, a carry-less multiplication instruction may be used to perform operations corresponding to verification of an encrypted message in accordance with GCM. Other embodiments are also described.

摘要翻译： 描述加速伽罗瓦计数器（GCM）计算的方法和装置。 在一个实施例中，可以使用无进位乘法指令来执行与根据GCM的加密消息的验证相对应的操作。 还描述了其他实施例。