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    MEMORY CELL WITH A FERROELECTRIC CAPACITOR INTEGRATED WITH A TRANSISTOR GATE
    2.
    发明公开
    MEMORY CELL WITH A FERROELECTRIC CAPACITOR INTEGRATED WITH A TRANSISTOR GATE 审中-公开

    公开(公告)号：EP4270396A2

    公开(公告)日：2023-11-01

    申请号：EP23198055.8

    申请日：2019-06-28

    申请人： INTEL Corporation

    发明人： MORRIS, Daniel H. ,  KIM, Seiyon ,  AVCI, Uygar E. ,  YOUNG, Ian A.

    IPC分类号： G11C11/22

    摘要： Described herein are ferroelectric (FE) memory cells that include transistors having gates with FE capacitors integrated therein. An example memory cell includes a transistor having a semiconductor channel material, a gate dielectric over the semiconductor material, a first conductor material over the gate dielectric, a FE material over the first conductor material, and a second conductor material over the FE material. The first and second conductor materials form, respectively, first and second capacitor electrodes of a capacitor, where the first and second capacitor electrodes are separated by the FE material (hence, a "FE capacitor"). Separating a FE material from a semiconductor channel material of a transistor with a layer of a gate dielectric and a layer of a first conductor material eliminates the FE-semiconductor interface that may cause endurance issues in some other FE memory cells.

    MULTIPLEXOR LOGIC FUNCTIONS IMPLEMENTED WITH CIRCUITS HAVING TUNNELING FIELD EFFECT TRANSISTORS (TFETS)
    5.
    发明公开
    MULTIPLEXOR LOGIC FUNCTIONS IMPLEMENTED WITH CIRCUITS HAVING TUNNELING FIELD EFFECT TRANSISTORS (TFETS) 审中-公开
    MIT SCHALTUNGEN MIT TUNNELFELDEFFEKTTRANSISTOREN（TFETS）实施物流多功能一体机

    公开(公告)号：EP3123522A1

    公开(公告)日：2017-02-01

    申请号：EP14886843.3

    申请日：2014-03-27

    申请人： Intel Corporation

    发明人： MORRIS, Daniel H. ,  AVCI, Uygar E. ,  RIOS, Rafael ,  YOUNG, Ian A.

    IPC分类号： H01L29/88 ,  H01L29/78 ,  H01L21/336

    CPC分类号： H03K17/693 ,  G11C5/066 ,  H01L27/092 ,  H01L29/7391 ,  H01L29/775 ,  H03K19/094 ,  H03K19/0948

    摘要： Multiplexor circuits with Tunneling field effect transistors (TFET) devices are described. For example, a multiplexor circuit includes a first set of tunneling field effect transistor (TFET) devices that are coupled to each other. The first set of TFET devices receive a first data input signal, a first select signal, and a second select signal. A second set of TFET devices are coupled to each other and receive a second data input signal, the first select signal, and the second select signal. An output terminal is coupled to the first and second set of TFETs. The output terminal generates an output signal of the multiplexor circuit.

    摘要翻译： 描述了具有隧道场效应晶体管（TFET）器件的多路复用器电路。 例如，多路复用器电路包括彼此耦合的第一组隧道场效应晶体管（TFET）器件。 第一组TFET器件接收第一数据输入信号，第一选择信号和第二选择信号。 第二组TFET器件彼此耦合并且接收第二数据输入信号，第一选择信号和第二选择信号。 输出端子耦合到第一和第二组TFET。 输出端产生多路复用器电路的输出信号。

    MEMORY CELL WITH A FERROELECTRIC CAPACITOR INTEGRATED WITH A TRANSISTOR GATE
    6.
    发明公开
    MEMORY CELL WITH A FERROELECTRIC CAPACITOR INTEGRATED WITH A TRANSISTOR GATE 审中-公开

    公开(公告)号：EP4270396A3

    公开(公告)日：2024-02-21

    申请号：EP23198055.8

    申请日：2019-06-28

    申请人： INTEL Corporation

    发明人： MORRIS, Daniel H. ,  KIM, Seiyon ,  AVCI, Uygar E. ,  YOUNG, Ian A.

    IPC分类号： G11C11/22

    摘要： Described herein are ferroelectric (FE) memory cells that include transistors having gates with FE capacitors integrated therein. An example memory cell includes a transistor having a semiconductor channel material, a gate dielectric over the semiconductor material, a first conductor material over the gate dielectric, a FE material over the first conductor material, and a second conductor material over the FE material. The first and second conductor materials form, respectively, first and second capacitor electrodes of a capacitor, where the first and second capacitor electrodes are separated by the FE material (hence, a "FE capacitor"). Separating a FE material from a semiconductor channel material of a transistor with a layer of a gate dielectric and a layer of a first conductor material eliminates the FE-semiconductor interface that may cause endurance issues in some other FE memory cells.

    FERROELECTRIC BASED MEMORY CELL WITH NON-VOLATILE RETENTION
    10.
    发明公开
    FERROELECTRIC BASED MEMORY CELL WITH NON-VOLATILE RETENTION 审中-公开
    基于铁电的存储器单元具有非易失性保持

    公开(公告)号：EP3304554A1

    公开(公告)日：2018-04-11

    申请号：EP15893518.9

    申请日：2015-05-28

    申请人： INTEL Corporation

    发明人： MORRIS, Daniel H. ,  AVCI, Uygar E. ,  YOUNG, Ian A.

    IPC分类号： G11C11/15

    CPC分类号： G11C14/0072 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C14/0027 ,  H01L27/11502

    摘要： Described is an apparatus which comprises: a first access transistor controllable by a write word-line (WWL); a second access transistor controllable by a read word-line (RWL); and a ferroelectric cell coupled to the first and second access transistors, wherein the ferroelectric cell is programmable via the WWL and readable via the RWL. Described is a method which comprises: driving a WWL, coupled to a gate terminal of a first access transistor, to cause the first access transistor to turn on; and driving a WBL coupled to a source/drain terminal of the first access transistor, the driven WBL to charge or discharge a storage node coupled to the first access transistor when the first access transistor is turned on, wherein the ferroelectric cell is coupled to the storage node and programmable according to the charged or discharged storage node.