公开(公告)号：EP1700338A1

公开(公告)日：2006-09-13

申请号：EP04815333.2

申请日：2004-12-21

申请人： INTEL CORPORATION

发明人： KAVALIEROS, Jack ,  BRASK, Justin, K. ,  DOCZY, Mark, L. ,  HARELAND, Scott, A. ,  METZ, Matthew, V. ,  BARNS, Chris, E. ,  CHAU, Robert, S.

IPC分类号： H01L21/8238

CPC分类号： H01L29/517 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/66545 ,  Y10S438/926

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods comprise providing a substrate comprising a first transistor structure comprising an n-type gate material and second transistor structure comprising a p-type gate material, selectively removing the n-type gate material to form a recess in the first gate structure, and then filling the recess with an n-type metal gate material.

公开(公告)号：EP1544161A1

公开(公告)日：2005-06-22

申请号：EP03766675.7

申请日：2003-07-31

申请人： Nikon Corporation

发明人： ISHIZUYA, Tohru, NIKON CORPORATION

IPC分类号： B81B3/00 ,  B81C1/00 ,  G02B26/08 ,  G02B26/02

CPC分类号： B81B3/0072 ,  B81C2201/0108 ,  G02B6/3518 ,  G02B6/3546 ,  G02B6/3572 ,  G02B6/3584 ,  G02B6/3596 ,  Y10S438/926

摘要： A three-dimensional structure element having a plurality of three-dimensional structural bodies and capable of being uniformly formed without producing a dispersion in shape of the three-dimensional structural bodies, comprising a substrate (11) and the three-dimensional structural bodies (1) disposed in predetermined effective area (20) on the substrate (11); the three-dimensional structural bodies (1) further comprising space parts formed in the clearances thereof from the substrate (11) by removing sacrificing layers, the substrate (11) further comprising a dummy area (21) having dummy structural bodies (33) so as to surround the effective area (20), the dummy structural body (33) further comprising space parts formed in the clearances thereof from the substrate (11) by removing the sacrificing layers, whereby since the dummy area (21) is heated merely to approx. the same temperature as the effective area (20) in an ashing process for removing the sacrificing layers to prevent a temperature distribution from occurring in the effective area (20).

摘要翻译： 具有三维结构体的多个A的三维结构元件和能够被均匀地形成，而不在所述三维结构体的形状生产的分散体，其包含一个基板（11）和所述三维结构体（1 ）设置在衬底（11）上的预定有效区域（20）; 所述三维结构体（1）还包括从所述衬底（11）其在间隙形成的空间部分通过除去牺牲层，所述衬底（11）还包括具有虚设结构体的虚设区域（21）（33），以便 以包围该有效区域（20），所述虚设结构体（33）还包括从所述衬底（11）通过去除所述牺牲层上在所述间隙形成的空间部分，由此由于虚拟区域（21）仅仅是为了加热 约。 相同的温度下的有效区域（20）到灰化用于去除牺牲层，以防止在有效区域（20）中发生的温度分布的过程。

公开(公告)号：EP1428262A2

公开(公告)日：2004-06-16

申请号：EP02786360.4

申请日：2002-09-20

申请人： Amberwave Systems Corporation

发明人： CURRIE, Matthew ,  LOCHTEFELD, Anthony ,  HAMMOND, Richard ,  FITZGERALD, Eugene, A.

IPC分类号： H01L29/36

CPC分类号： H01L29/1054 ,  H01L29/105 ,  H01L29/161 ,  H01L29/36 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7842 ,  Y10S438/926

摘要： Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or "FETs") that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

公开(公告)号：EP0933811A3

公开(公告)日：1999-09-08

申请号：EP98310800.2

申请日：1998-12-30

申请人： International Business Machines Corporation ,  SIEMENS AKTIENGESELLSCHAFT

发明人： Jaso, Mark A. ,  Schnabel, Rainer F.

IPC分类号： H01L21/768 ,  H01L21/321

CPC分类号： H01L21/3212 ,  Y10S438/926

摘要： A method and apparatus is provided for planarizing damascene metallic circuit patterns of a plurality of discrete integrated circuit chips on a metal coated silicon wafer wherein the circuitry on the chips on the wafer are either designed to be within a defined high metal density circuit range and low density metal circuit range and/or to provide dummy circuitry in the damascene process to provide a substantially uniform circuit density over the chip and the wafer surface. It is preferred that each chip on the surface of the wafer be divided into a plurality of regions and that each region be provided with dummy metallization, if necessary, to provide a relatively uniform circuit density in that region and consequently on the wafer surface. The invention also contemplates adding dummy circuitry to the periphery of the wafer in areas which are not formed into chips (chip fragments). The invention also provides semiconductor wafers made using the method and/or apparatus of the invention.

摘要翻译： 提供了一种用于平坦化金属涂覆的硅晶片上的多个分立集成电路芯片的镶嵌金属电路图案的方法和装置，其中晶片上的芯片上的电路被设计成处于限定的高金属密度电路范围内并且低 密度金属电路范围和/或在镶嵌工艺中提供虚设电路以在芯片和晶片表面上提供基本均匀的电路密度。 如果需要，晶片表面上的每个芯片优选被分成多个区域，并且每个区域都设置有虚拟金属化部分，以在该区域中并因此在晶片表面上提供相对均匀的电路密度。 本发明还考虑在未形成芯片（芯片碎片）的区域中向晶片的外围添加虚拟电路。 本发明还提供使用本发明的方法和/或设备制造的半导体晶片。

公开(公告)号：EP0463165B1

公开(公告)日：2002-12-04

申请号：EP90913222.7

申请日：1990-09-07

申请人： OHMI, Tadahiro ,  CANON KABUSHIKI KAISHA

发明人： OHMI, Tadahiro ,  MIYAWAKI, Mamoru

IPC分类号： H01L29/43 ,  H01L29/732 ,  H01L29/737 ,  H01L29/78 ,  H01L23/532 ,  H01L21/314 ,  H01L21/316 ,  H01L21/60 ,  H01L21/331 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L21/31683 ,  H01L29/1033 ,  H01L29/41775 ,  H01L29/42304 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/66628 ,  H01L29/7375 ,  H01L29/7378 ,  H01L2924/0002 ,  Y10S148/10 ,  Y10S438/926 ,  Y10S438/951 ,  H01L2924/00

摘要： An element which includes a first film containing no impurity particles due to spontaneous oxidization or residual resist at its surface, and an electrically conductive material layer formed on a surface in contact with the surface of said first film. On the surface of the electrically conductive material layer is formed an insulating compound film as a result of surface reaction with the electrically conductive material layer, and on the surface of said first film is formed a desired second film that is necessary for constituting the element.

摘要翻译： 它包括一个第一膜含由于自发氧化或没有残留杂质微粒的抗蚀剂在其表面上，并且在与所述第一部电影的表面接触的表面上形成导电材料层的元素。 在导电材料层的表面上形成绝缘化合物薄膜作为与所述导电材料层，和在所述第一部电影的表面表面反应的结果形成所希望的第二电影的确实是必要的构成元件。

公开(公告)号：EP1196948A2

公开(公告)日：2002-04-17

申请号：EP00939336.4

申请日：2000-05-24

申请人： MOTOROLA, INC.

发明人： TRAVIS, Edward, O. ,  DENGI, Aykut ,  CHHEDA, Sejal ,  YU, Tat-Kwan ,  ROBERTON, Mark, S. ,  TIAN, Ruiqi

IPC分类号： H01L21/3105 ,  H01L21/321

CPC分类号： H01L21/31053 ,  H01L21/3212 ,  Y10S438/926

摘要： Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature patterns can be specifically tailored to a semiconductor device and polishing conditions used in forming the semiconductor device. When designing an integrated circuit, polishing effects for the active features can be predicted. After polishing dummy feature pattern(s) are placed into the layout, the planarity can be examined on a local level (a portion but not all of the device) and a more global level (all of the device, devices corresponding to a reticle field, or even an entire wafer).

公开(公告)号：EP0688049B1

公开(公告)日：2001-12-19

申请号：EP95303504.5

申请日：1995-05-24

申请人： AT&T Corp.

发明人： Chiu, Tzu-Yin ,  Erceg, Frank Michael ,  Krafty, Francis Anthony ,  Liu, Te-Yin Mark ,  Possanza, William A. ,  Sung, Janmye

IPC分类号： H01L21/8248 ,  H01L21/3105 ,  H01L21/311 ,  H01L27/06

CPC分类号： H01L21/76229 ,  H01L21/8249 ,  H01L27/0623 ,  Y10S148/106 ,  Y10S148/123 ,  Y10S148/151 ,  Y10S438/926 ,  Y10S438/942

公开(公告)号：EP0838849A3

公开(公告)日：1998-06-10

申请号：EP97308619.2

申请日：1997-10-27

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Rodder, Mark S.

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/41783 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66628 ,  Y10S438/926

摘要： A method for forming a MOSFET (200) using a disposable gate. A disposable gate (220) having at least two materials that may be etched selectively with respect to each other is formed on a substrate (202). A sidewall dielectric (215) is formed on the sidewalls of the disposable gate (220). The composition of the disposable gate materials (222, 223 and 224) and the sidewall dielectric (215) are chosen such that the disposable gate (220) may be removed selectively with respect to the sidewall dielectric (215). A dielectric layer (214) is then deposited over the structure and a portion of the dielectric layer (214) is removed to expose the disposable gate (220) (e.g. using CMP or an etch-back). The composition of the dielectric layer (214) is chosen such that (1) the dielectric layer (214) may be removed selectively with respect to the sidewall dielectric (215) and (2) a layer of the disposable gate (220) may be removed selectively with respect to the dielectric layer (214). The disposable gate (220) is then removed and the gate dielectric (210) and gate electrode (212) are formed.

摘要翻译： 一种使用一次性门形成MOSFET（200）的方法。 在衬底（202）上形成具有至少两种可相对于彼此选择性蚀刻的材料的一次性门（220）。 侧壁电介质（215）形成在一次性门（220）的侧壁上。 一次性栅极材料（222,223和224）和侧壁电介质（215）的组成被选择成使得可相对于侧壁电介质（215）选择性地移除一次性栅极（220）。 然后在该结构上沉积电介质层（214），并且去除该电介质层（214）的一部分以暴露该一次性栅极（220）（例如使用CMP或回蚀刻）。 选择电介质层（214）的组成使得（1）可以相对于侧壁电介质（215）选择性地去除电介质层（214），并且（2）一次性栅极（220）的层可以是 相对于介电层（214）选择性地去除。 然后去除一次性栅极（220），并形成栅极电介质（210）和栅极电极（212）。

公开(公告)号：EP0818810A3

公开(公告)日：1998-03-04

申请号：EP97111065.5

申请日：1997-07-02

申请人： TRW INC.

发明人： Lammert, Michael

IPC分类号： H01L21/331 ,  H01L29/737

CPC分类号： H01L29/66318 ,  Y10S148/072 ,  Y10S148/10 ,  Y10S438/926 ,  Y10S438/944 ,  Y10S438/945 ,  Y10S438/951

摘要： A method for controlling the spacing between the emitter mesa and the base ohmic metal of a heterojunction bipolar transistor (HBT) to obtain a relatively high gain (β) with a low-parasitic base resistance. In a first method, after the emitter, base and collector layers are epitaxially grown on a substrate, a sacrificial layer is deposited on top of the emitter layer. The emitter mesa is patterned with a photoresist using conventional lithography. Subsequently, the sacrificial layer is etched to produce an undercut. The emitter layer is then etched and a photoresist is applied over the first photoresist used to pattern the emitter mesa, as well as the entire device. The top layer of photoresist is patterned with a conventional process for lift-off metalization, such that the final resist profile has a re-entrant slope. The base ohmic metal is deposited and then lifted off by dissolving both the second layer of photoresist, as well as the original photoresist over the emitter mesa. The sacrificial layer is stripped using an isotropic etch leaving a base ohmic metal region surrounding an emitter mesa at a spacing that is determined by the initial undercut of the sacrificial layer. In an alternate embodiment of the invention, a method is disclosed for controlling the spacing between the base ohmic metal and an emitter ohmic metal.

摘要翻译： 用于控制异质结双极晶体管（HBT）的发射极台面和基极欧姆金属之间的间隔以获得具有低寄生基极电阻的较高增益（β）的方法。 在第一种方法中，在发射极（26）之后，在衬底（20）上外延生长基极（24）和集电极（22）层，牺牲层（28）沉积在发射极层（26）的顶部。 使用常规光刻法，用光致抗蚀剂对发射极台面（32）进行图案化。 随后，牺牲层（28）被蚀刻以产生底切。 然后蚀刻发射极层（26），并且在用于图案化发射极台面（32）的第一光致抗蚀剂以及整个器件上施加光致抗蚀剂。 用常规的用于剥离金属化的方法对光致抗蚀剂的顶层进行图案化，使得最终抗蚀剂轮廓具有重入斜率。 沉积基极欧姆金属（48），然后通过将第二层光致抗蚀剂以及原始光致抗蚀剂溶解在发射台台面（32）上而提起。 使用各向同性蚀刻剥离牺牲层（28），以由牺牲层的初始底切确定的间隔留下围绕发射器台面的基极欧姆金属区域。 在本发明的替代实施例中，公开了一种用于控制基极欧姆金属和发射极欧姆金属之间的间隔的方法。

公开(公告)号：EP0735583A3

公开(公告)日：1997-05-21

申请号：EP96302137.3

申请日：1996-03-27

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Fukuhara, Hideyuki ,  Ashigaki, Shigeo

IPC分类号： H01L23/525

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  Y10S148/055 ,  Y10S438/926 ,  H01L2924/00

摘要： A fuse link 16 is formed of a portion of a top level of patterned metal conductor in a multilevel conductor integrated circuit 10. A deposited layer of oxide material 26 covers the fuse link. Radiant energy from such as a laser 36 is directed through the oxide material 26 to heat and open the fuse link 16. Layers of deposited protective oxide 28 and PIX 30 then cover the fuse link and layer of oxide material. One photoprocessing step is avoided by locating the fuse link 16 and bond pad 22, both made from the top layer of conductive material, at different levels. The blanket etch then exposes the bond pad 22 while leaving the fuse link 16 covered. The fuse link can be formed down in a step 38 or the bond pad 22 can be formed above such as a group of memory cells 80. The bond pad 22 and fuse link 16 also can be formed at the same level with other process procedures.